參數(shù)資料
型號: ADSP-21266
廠商: Analog Devices, Inc.
英文描述: SHARC Embedded Processor
中文描述: SHARC處理器嵌入式處理器
文件頁數(shù): 25/44頁
文件大?。?/td> 426K
代理商: ADSP-21266
ADSP-21266
Rev. B
|
Page 25 of 44
|
May 2005
Memory Read—Parallel Port
The specifications in
Table 20
,
Table 21
,
Figure 17
, and
Figure 18
are for asynchronous interfacing to memories (and
memory-mapped peripherals) when the ADSP-21266 is access-
ing external memory space.
Table 20. 8-Bit Memory Read Cycle
Parameter
Timing Requirements
t
DRS
t
DRH
t
DAD
Min
Max
Unit
Address/Data 7–0 Setup Before RD High
Address/Data 7–0 Hold After RD High
Address 15–8 to Data Valid
3.3
0
ns
ns
ns
D + 0.5 × t
CCLK
– 3.5
Switching Characteristics
t
ALEW
t
ALERW
t
ADAS
t
ADAH
t
ALEHZ
t
RW
t
ADRH
D = (data cycle duration) × t
CCLK
H = t
CCLK
(if a hold cycle is specified, else H = 0)
ALE Pulse Width
ALE Deasserted to Read/Write Asserted
Address/Data 15–0 Setup Before ALE Deasserted
1
Address/Data 15–0 Hold After ALE Deasserted
1
ALE Deasserted
1
to Address/Data[7:0] In High Z
RD Pulse Width
Address/Data 15–8 Hold After RD High
2 × t
CCLK
– 2
1 × t
CCLK
– 0.5
2.5 × t
CCLK
– 2.0
0.5 × t
CCLK
– 0.8
0.5 × t
CCLK
– 0.8
D – 2
0.5 × t
CCLK
– 1 + H
ns
ns
ns
ns
ns
ns
ns
0.5 × t
CCLK
+ 2.0
1
On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.
Figure 17. 8-Bit Memory Read Cycle
VALID DATA
AD15-8
VALID ADDRESS
VALID ADDRESS
t
ADAS
VALID ADDRESS
AD7-0
t
ALEW
ALE
RD
t
RW
WR
t
ADAH
t
ADRH
t
ALEHZ
t
DRS
t
DRH
t
DAD
t
ALERW
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