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參數(shù)資料
| 型號： | ADSP-21160NCB-100 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 36/48頁 |
| 文件大小： | 0K |
| 描述： | IC DSP CONTROLLER 32BIT 400BGA |
| 產(chǎn)品培訓(xùn)模塊： | SHARC Processor Overview |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SHARC® |
| 類型： | 浮點(diǎn) |
| 接口： | 主機(jī)接口，連接端口，串行端口 |
| 時鐘速率： | 100MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 512kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.90V |
| 工作溫度： | -40°C ~ 100°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 400-BBGA |
| 供應(yīng)商設(shè)備封裝： | 400-PBGA（27x27） |
| 包裝： | 托盤 |
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–41–
REV. 0
ADSP-21160N
where:
P
EXT is from Table 30
P
INT is IDDINT × 1.9 V, using the calculation IDDINT listed in
Power Dissipation on Page 40
P
PLL is AIDD × 1.9 V, using the value for AIDD listed in
ABSOLUTE MAXIMUM RATINGS on Page 15
Note that the conditions causing a worst-case PEXT are different
from those causing a worst-case PINT. Maximum PINT cannot
occur while 100% of the output pins are switching from all ones
to all zeros. Note also that it is not common for an application to
have 100% or even 50% of the outputs switching simultaneously.
Test Conditions
The test conditions for timing parameters appearing in ADSP-
21160N specifications on Page 14 include output disable time,
output enable time, and capacitive loading.
Output Disable Time
Output pins are considered to be disabled when they stop driving,
go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by
V is dependent on the capacitive load, C
L and the
load current, IL. This decay time can be approximated by the
following equation:
tDECAY = (CL
V)/I
L
The output disable time tDIS is the difference between tMEASURED
interval from when the reference signal switches to when the
output voltage decays
V from the measured output high or
output low voltage. tDECAY is calculated with test loads CL and IL,
and with
V equal to 0.5 V.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start
driving. The output enable time tENA is the interval from when a
reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram (Figure 28). If multiple
pins (such as the data bus) are enabled, the measurement value
is that of the first pin to start driving.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose
V
to be the difference between the ADSP-21160N’s output voltage
and the input threshold for the device requiring the hold time. A
typical
V will be 0.4 V. C
L is the total bus capacitance (per data
line), and IL is the total leakage or three-state current (per data
line). The hold time will be tDECAY plus the minimum disable time
(i.e., tDATRWH for the write cycle).
Table 30. External Power Calculations (3.3 V Device)
Pin Type
No. of Pins
% Switching
× C
× f
× VDD
2
= PEXT
Address
15
50
× 44.7 pF
× 24 MHz
× 10.9 V
= 0.088 W
MS0
1
0
× 44.7 pF
× 24 MHz
× 10.9 V
= 0.000 W
WRx
2
× 44.7 pF
× 24 MHz
× 10.9 V
= 0.023 W
Data
64
50
× 14.7 pF
× 24 MHz
× 10.9 V
= 0.123 W
CLKOUT
1
× 4.7 pF
× 48 MHz
× 10.9 V
= 0.003 W
PEXT = 0.237 W
Figure 28. Output Enable/Disable
Figure 29. Equivalent Device Loading for AC
Measurements (Includes All Fixtures)
Figure 30. Voltage Reference Levels for AC Measurements
(Except Output Enable/Disable)
REFERENCE
SIGNAL
tDIS
OUTPUT STARTS
DRIVING
VOH (MEASURED) – V
VOL (MEASURED) + V
tMEASURED
VOH (MEASURED)
VOL (MEASURED)
2.0V
1.0V
HIGH IMPEDANCE STATE.
TEST CONDITIONS CAUSE THIS VOLTAGE
TO BE APPROXIMATELY 1.5V
OUTPUT STOPS
DRIVING
tDECAY
tENA
1.5V
30pF
TO
OUTPUT
PIN
50
INPUT
OR
OUTPUT
1.5V
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| ADSP-21160NCB-TBD | 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer |
| ADSP-21160NCBZ-100 | 功能描述:IC DSP CONTROLLER 32BIT 400-PBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-21160NCE-100 | 制造商:Analog Devices 功能描述: |
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| ADSP-21160NKB-95 | 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer |
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