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| 型號： | ADSP-21160NCB-100 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 35/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CONTROLLER 32BIT 400BGA |
| 產(chǎn)品培訓模塊： | SHARC Processor Overview |
| 標準包裝： | 1 |
| 系列： | SHARC® |
| 類型： | 浮點 |
| 接口： | 主機接口，連接端口，串行端口 |
| 時鐘速率： | 100MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 512kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.90V |
| 工作溫度： | -40°C ~ 100°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 400-BBGA |
| 供應(yīng)商設(shè)備封裝： | 400-PBGA（27x27） |
| 包裝： | 托盤 |
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ADSP-21160N
–40–
REV. 0
Output Drive Currents
Figure 27 shows typical I–V characteristics for the output drivers
of the ADSP-21160N. The curves represent the current drive
capability of the output drivers as a function of output voltage.
Power Dissipation
Total power dissipation has two components, one due to internal
circuitry and one due to the switching of external output drivers.
Internal power dissipation is dependent on the instruction
execution sequence and the data operands involved. Using the
current specifications (IDD-INPEAK, IDD-INHIGH, IDD-INLOW, IDD-IDLE)
from Electrical Characteristics on Page 14 and the current-
versus-operation information in Table 29, engineers can
estimate the ADSP-21160N’s internal power supply (VDDINT)
input current for a specific application, according to the formula.
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
the number of output pins that switch during each
cycle (O)
the maximum frequency at which they can switch (f)
their load capacitance (C)
their voltage swing (V
DD)
and is calculated by:
PEXT = O × C × VDD
2 × f
The load capacitance should include the processor’s package
capacitance (CIN). The switching frequency includes driving the
load high and then back low. Address and data pins can drive high
and low at a maximum rate of 1/(2tCK). The write strobe can
switch every cycle at a frequency of 1/tCK. Select pins switch at
1/(2tCK), but selects can switch on each cycle.
Example: Estimate PEXT with the following assumptions:
A system with one bank of external data memory—asyn-
chronous RAM (64-bit)
Four 64K × 16 RAM chips are used, each with a load
of 10 pF
External data memory writes occur every other cycle, a
rate of 1/(2 tCK), with 50% of the pins switching
The bus cycle time is 50 MHz (t
CK = 20 ns).
The PEXT equation is calculated for each class of pins that
can drive, as shown in Table 30.
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation:
PTOTAL = PEXT + PINT + PPLL
Figure 27. Typical Drive Currents
SWEEP (VDDEXT)VOLTAGE – V
03.5
0.5
1
1.5
2
2.5
3
S
O
U
R
C
E
(V
D
E
X
T
)
C
U
R
E
N
T
–
m
A
–80
–60
–40
–20
0
20
40
60
80
VDDEXT = 3.47V, –45°C
VDDEXT =3.47V, –45°C
VDDEXT =3.3V, 25°C
VDDEXT = 3.11V, 115°C
VOH
VDDEXT = 3.11V, 115°C
VDDEXT = 3.3V, 25°C
VOL
% Peak
I
DD-INPEAK
×
% High
I
DD-INHIGH
×
% Low
I
DD-INLOW
×
+ % Idle
I
DD-IDLE
×
I
DDINT
-----------------------------------------------------
Table 29. ADSP-21160N Operation Types vs. Input Current
Operation
Peak Activity
1
High Activity
Low Activity
Instruction Type
Multifunction
Single Function
Instruction Fetch
Cache
Internal Memory
Core Memory Access
2
2 per tCK Cycle
(DM
64 and PM
64)
1 per tCK Cycle
(DM
64)
None
Internal Memory DMA
1 per 2 tCCLK Cycles
None
External Memory DMA
1 per External Port Cycle ( 64)
1 per External Port Cycle (
64)
None
Data Bit Pattern for Core
Memory Access and DMA
Worst Case
Random
N/A
1 Peak Activity=IDD-INPEAK, High Activity=IDD-INHIGH, and Low Activity=IDD-INLOW. The state of the PEYEN bit (SIMD versus SISD mode) does not
influence these calculations.
2 These assume a 2:1 core clock ratio. For more information on ratios and clocks (tCK and tCCLK), see the timing ratio definitions on Page 16.
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| ADSP-21160NCB-TBD | 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer |
| ADSP-21160NCBZ-100 | 功能描述:IC DSP CONTROLLER 32BIT 400-PBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-21160NCE-100 | 制造商:Analog Devices 功能描述: |
| ADSP-21160NKB-100 | 功能描述:IC DSP CONTROLLER 32BIT 400BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21160NKB-95 | 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer |
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