參數(shù)資料
型號: ADSP-21065LKCA-264
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號處理
英文描述: DSP Microcomputer
中文描述: 32-BIT, 33.33 MHz, OTHER DSP, PBGA196
封裝: CHIP SCALE, MS-034AAE-1, BGA-196
文件頁數(shù): 37/44頁
文件大?。?/td> 331K
代理商: ADSP-21065LKCA-264
REV. B
ADSP-21065L
–37–
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
50 pF on all pins. The delay and hold specifications given
should be derated by a factor of l.8 ns/50 pF for loads other
than the nominal value of 50 pF. Figure 28 and Figure 29 show
how output rise time varies with capacitance. Figure 30 shows
graphically how output delays and hold vary with load capaci-
tance. (Note that this graph or derating does not apply to output
disable delays; see the previous section Output Disable time
under Test Conditions.) The graphs of Figure 28, Figure 29
and Figure 30 may not be linear outside the ranges shown.
LOAD CAPACITANCE
pF
0
0
200
20
R
40
60
80
100
120
140
160
180
2
RISE TIME
FALL TIME
4
6
8
10
12
14
16
18
Figure 28. Typical Rise and Fall Time (10%–90% V
DD
)
LOAD CAPACITANCE
pF
8.0
4.0
00
200
20
R
40
60
80
100
120
140
160
180
7.0
6.0
2.0
1.0
5.0
3.0
RISE TIME
FALL TIME
Figure 29. Typical Rise and Fall Time (0.8 V–2.0 V)
LOAD CAPACITANCE
pF
O
5
2
0
140
20
40
60
80
100
120
4
3
2
1
0
1
160
180
200
6
Figure 30. Typical Output Delay or Hold
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