參數(shù)資料
型號(hào)： ADSP-21065LKCA-264
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： DSP Microcomputer
中文描述： 32-BIT, 33.33 MHz, OTHER DSP, PBGA196
封裝： CHIP SCALE, MS-034AAE-1, BGA-196
文件頁數(shù)： 32/44頁
文件大?。?/td> 331K
代理商： ADSP-21065LKCA-264
REV. B
ADSP-21065L
–32–
Serial Ports
Parameter
Min
Max
Units
External Clock
Timing Requirements:
t
SFSE
t
HFSE
t
SDRE
t
HDRE
t
SCLKW
t
SCLK
Internal Clock
Timing Requirements:
t
SFSI
t
HFSI
t
SDRI
t
HDRI
External or Internal Clock
Switching Characteristics:
t
DFSE
t
HOFSE
External Clock
Switching Characteristics:
t
DFSE
t
HOFSE
t
DDTE
t
HDTE
Internal Clock
Switching Characteristics:
t
DFSI
t
HOFSI
t
DDTI
t
HDTI
t
SCLKIW
Enable and Three-State
Switching Characteristics:
t
DTENE
t
DDTTE
t
DTENI
t
DDTTI
t
DCLK
t
DPTR
External Late Frame Sync
t
DDTLFSE
TFS/RFS Setup Before TCLK/RCLK
1
TFS/RFS Hold After TCLK/RCLK
1
Receive Data Setup Before RCLK
1
Receive Data Hold After RCLK
1
TCLK/RCLK Width
TCLK/RCLK Period
4.0
4.0
1.5
4.0
9.0
t
CK
ns
ns
ns
ns
ns
ns
TFS Setup Before TCLK
2
; RFS Setup Before RCLK
1
TFS/RFS Hold After TCLK/RCLK
1
Receive Data Setup Before RCLK
1
Receive Data Hold After RCLK
1
8.0
1.0
3.0
3.0
ns
ns
ns
ns
RFS Delay After RCLK (Internally Generated RFS)
2
RFS Hold After RCLK (Internally Generated RFS)
2
13.0
ns
ns
3.0
TFS Delay After TCLK (Internally Generated TFS)
2
TFS Hold After TCLK (Internally Generated TFS)
2
Transmit Data Delay After TCLK
2
Transmit Data Hold After TCLK
2
13.0
ns
ns
ns
ns
3.0
12.5
4.0
TFS Delay After TCLK (Internally Generated TFS)
2
TFS Hold After TCLK (Internally Generated TFS)
2
Transmit Data Delay After TCLK
2
Transmit Data Hold After TCLK
2
TCLK/RCLK Width
4.5
ns
ns
ns
ns
ns
–1.5
7.5
0.0
(t
SCLK
/2) – 2.5
(t
SCLK
/2) + 2.5
Data Enable from External TCLK
2
Data Disable from External RCLK
2
Data Enable from Internal TCLK
2
Data Disable from Internal TCLK
2
TCLK/RCLK Delay from CLKIN
SPORT Disable After CLKIN
5.0
ns
ns
ns
ns
ns
ns
10.0
0.0
3.0
18.0 + 6 DT
14.0
Data Delay from Late External TFS or External RFS
with MCE = 1, MFD = 0
3, 4
Data Enable from late FS or MCE = 1, MFD = 0
3, 4
Data Delay from TCLK/RCLK for Late External
TFS or External RFS with MCE = 1, MFD = 0
3, 4
Data Enable from RCLK/TCLK for Late External FS or
MCE = 1, MFD = 0
3, 4
10.5
ns
ns
t
DTENLFSE
t
DDTLSCK
3.5
12.0
ns
t
DTENLSCK
4.5
ns
NOTES
To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame
sync setup-and-hold, 2) data delay and data setup-and-hold, and 3) SCLK width.
1
Referenced to sample edge.
2
Referenced to drive edge.
3
MCE = 1, TFS enable and TFS valid follow t
DDTENFS
and t
DDTLFSE.
4
If external RFS/TFS setup to RCLK/TCLK > t
SCLK
/2 then t
DDTLSCK
and t
DTENLSCK
apply; otherwise t
DDTLFSE
and t
DTENLFS
apply.
*Word selected timing for I
S mode is the same as TFS/RFS timing (normal framing only).
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