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參數(shù)資料
| 型號(hào)： | ADSP-21065LKCA-264 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | DSP Microcomputer |
| 中文描述： | 32-BIT, 33.33 MHz, OTHER DSP, PBGA196 |
| 封裝： | CHIP SCALE, MS-034AAE-1, BGA-196 |
| 文件頁(yè)數(shù)： | 16/44頁(yè) |
| 文件大?。?/td> | 331K |
| 代理商： | ADSP-21065LKCA-264 |
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REV. B
ADSP-21065L
–16–
Memory Read—Bus Master
Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN.
These specifications apply when the ADSP-21065L is the bus master when accessing external memory space. These switching char-
acteristics also apply for bus master synchronous read/write timing (see Synchronous Read/Write—Bus Master below). If these tim-
ing requirements are met, the synchronous read/write timing can be ignored (and vice versa). An exception to this is the ACK pin
timing requirements as described in the note below.
Parameter
Min
Max
Units
Timing Requirements:
t
DAD
t
DRLD
t
HDA
t
HDRH
t
DAAK
t
DSAK
Address, Selects Delay to Data Valid
1, 2
RD
Low to Data Valid
1
Data Hold from Address Selects
3
Data Hold from
RD
High
3
ACK Delay from Address, Selects
2, 3
ACK Delay from
RD
Low
3
28.0 + 32 DT + W
24.0 + 26 DT + W
ns
ns
ns
ns
ns
ns
0.0
0.0
24.0 + 30 DT + W
19.5 + 24 DT + W
Switching Characteristics:
t
DRHA
t
DARL
t
RW
t
RWR
t
RDGL
Address, Selects Hold After
RD
High
Address, Selects to
RD
Low
2
RD
Pulsewidth
RD
High to
WR
,
RD
Low
RD
High to
DMAG
x Low
–1.0 + H
3.0 + 6 DT
25.0 + 26 DT + W
4.5 + 6 DT + HI
11.0 +12 DT + HI
ns
ns
ns
ns
ns
W = (number of wait states specified in WAIT register)
×
t
CK
.
HI = t
CK
(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
H = t
CK
(if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
NOTES
1
Data Delay/Setup: User must meet t
or to t
or synchronous specification t
SSDATI
.
2
The falling edge of
MS
x,
SW
,
BMS
, are referenced.
3
ACK is not sampled on external memory accesses that use the
Internal
wait state mode. For the first CLKIN cycle of a new external memory access, ACK must be
valid by t
or t
or synchronous specification t
for wait state modes
External
,
Either
, or
Both
(
Both
, if the internal wait state is zero). For the second and
subsequent cycles of a wait stated external memory access, synchronous specifications t
SACKC
and t
HACKC
must be met for wait state modes
External
,
Either
, or
Both
(
Both
, after internal wait states have completed).
WR
ACK
DATA
RD
ADDRESS
MSx
,
SW
BMS
t
DARL
t
RW
t
DAAK
t
RWR
t
DRHA
t
DSAK
DMAG
t
HDRH
t
RDGL
t
DRLD
t
DAD
t
HDA
Figure 11. Memory Read—Bus Master
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