參數資料
型號： ADSP-21065LKCA-264
廠商： ANALOG DEVICES INC
元件分類： 數字信號處理
英文描述： DSP Microcomputer
中文描述： 32-BIT, 33.33 MHz, OTHER DSP, PBGA196
封裝： CHIP SCALE, MS-034AAE-1, BGA-196
文件頁數： 14/44頁
文件大小： 331K
代理商： ADSP-21065LKCA-264
REV. B
ADSP-21065L
–14–
Switching Characteristics
specify how the processor changes its signals. You have no control over this timing—circuitry external to the
processor must be designed for compatibility with these signal characteristics. Switching characteristics tell you what the processor
will do in a given circumstance. You can also use switching characteristics to ensure that any timing requirement of a device con-
nected to the processor (such as memory) is satisfied.
Timing Requirements
apply to signals that are controlled by circuitry external to the processor, such as the data input for a read opera-
tion. Timing requirements guarantee that the processor operates correctly with other devices.
(O/D) = Open Drain
(A/D) = Active Drive
66 MHz
60 MHz
Parameter
Min
Max
Min
Max
Units
Clock Input
Timing Requirements:
t
CK
t
CKL
t
CKH
t
CKRF
CLKIN Period
CLKIN Width Low
CLKIN Width High
CLKIN Rise/Fall (0.4 V–2.0 V)
30.00
7.0
5.0
100
33.33
7.0
5.0
100
ns
ns
ns
ns
3.0
3.0
CLKIN
t
CKH
t
CK
t
CKL
Figure 7. Clock Input
Parameter
Min
Max
Units
Reset
Timing Requirements:
t
WRST
t
SRST
RESET
Pulsewidth Low
1
RESET
Setup Before CLKIN High
2
2 t
CK
23.5 + 24 DT t
CK
ns
ns
NOTES
1
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 3000 CLKIN cycles while
RESET
is
low, assuming stable V
and CLKIN (not including start-up time of external clock oscillator).
2
Only required if multiple ADSP-2106xs must come out of reset synchronous to CLKIN with program counters (PC) equal (i.e., for a SIMD system). Not required
for multiple ADSP-2106xs communicating over the shared bus (through the external port), because the bus arbitration logic synchronizes itself automatically after
reset.
CLKIN
RESET
t
WRST
t
SRST
Figure 8. Reset
Parameter
Min
Max
Units
Interrupts
Timing Requirements:
t
SIR
t
HIR
t
IPW
IRQ
2-0 Setup Before CLKIN High or Low
1
IRQ
2-0 Hold Before CLKIN High or Low
1
IRQ
2-0 Pulsewidth
2
11.0 + 12 DT
ns
ns
ns
0.0 + 12 DT
2.0 + t
CK
/2
NOTES
1
Only required for
IRQ
x recognition in the following cycle.
2
Applies only if t
SIR
and t
HIR
requirements are not met.
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