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參數(shù)資料
| 型號： | ADSP-21061KS-200 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | ADSP-2106x SHARC DSP Microcomputer Family |
| 中文描述： | 48-BIT, 50 MHz, OTHER DSP, PQFP240 |
| 封裝： | MQFP-240 |
| 文件頁數(shù)： | 9/47頁 |
| 文件大?。?/td> | 367K |
| 代理商： | ADSP-21061KS-200 |
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ADSP-21061/ADSP-21061L
–9–
REV. B
PIN DESCRIPTIONS
ADSP-21061 pin definitions are listed below. Inputs identified
as synchronous (S) must meet timing requirements with respect
to CLKIN (or with respect to TCK for TMS, TDI). Inputs
identified as asynchronous (A) can be asserted asynchronously
to CLKIN (or to TCK for
TRST
).
Unused inputs should be tied or pulled to IVDD or IGND,
except for ADDR
31-0
, DATA
47-0
, FLAG
3-0
,
SW
and inputs that
have internal pull-up or pull-down resistors (
CPA
, ACK, DTx,
DRx, TCLKx, RCLKx, TMS and TDI)—these pins can be left
floating. These pins have a logic-level hold circuit that prevents
the input from floating internally.
I = Input
S = Synchronous
(O/D) = Open Drain
O = Output
G = Ground
(A/D) = Active Drive
T = Three-State (when
SBTS
is asserted, or when the
ADSP-2106x is a bus slave)
P = Power Supply
A = Asynchronous
PIN FUNCTION DESCRIPTIONS
Pin
Type
Function
ADDR
31-0
I/O/T
External Bus Address
. The ADSP-21061 outputs addresses for external memory and peripherals
on these pins. In a multiprocessor system the bus master outputs addresses for read/writes of the
internal memory or IOP registers of other ADSP-2106xs. The ADSP-21061 inputs addresses when a
host processor or multiprocessing bus master is reading or writing its internal memory or IOP registers.
External Bus Data
. The ADSP-21061 inputs and outputs data and instructions on these pins.
The external data bus transfers 32-bit single-precision floating-point data and 32-bit fixed-point
data over Bits 47-16. 40-bit extended-precision floating-point data is transferred over Bits 47-8 of
the bus. 16-bit short word data is transferred over Bits 31-16 of the bus. Pull-up resistors on un-
used DATA pins are not necessary.
Memory Select Lines
. These lines are asserted (low) as chip selects for the corresponding banks
of external memory. Memory bank size must be defined in the ADSP-21061’s system control regis-
ter (SYSCON). The
MS
3-0
lines are decoded memory address lines that change at the same time as
the other address lines. When no external memory access is occurring the
MS
3-0
lines are inactive;
they are active, however, when a conditional memory access instruction is executed, whether or not the
condition is true.
MS
0
can be used with the PAGE signal to implement a bank of DRAM memory
(Bank 0). In a multiprocessor system the
MS
3-0
lines are output by the bus master.
Memory Read Strobe
. This pin is asserted (low) when the ADSP-21061 reads from external
memory devices or from the internal memory of other ADSP-21061s. External devices (including
other ADSP-21061s) must assert
RD
to read from the ADSP-21061’s internal memory. In a multi-
processor system
RD
is output by the bus master and is input by all other ADSP-21061s.
Memory Write Strobe
. This pin is asserted (low) when the ADSP-21061 writes to external memory
devices or to the internal memory of other ADSP-21061s. External devices must assert
WR
to write to
the ADSP-21061’s internal memory. In a multiprocessor system
WR
is output by the bus master and is
input by all other ADSP-21061s.
DRAM Page Boundary
. The ADSP-21061 asserts this pin to signal that an external DRAM page
boundary has been crossed. DRAM page size must be defined in the ADSP-21061’s memory con-
trol register (WAIT). DRAM can only be implemented in external memory Bank 0; the PAGE
signal can only be activated for Bank 0 accesses. In a multiprocessor system PAGE is output by the
bus master.
Address Clock
for synchronous external memories. Addresses on ADDR
31-0
are valid before the
rising edge of ADRCLK. In a multiprocessing system ADRCLK is output by the bus master.
Synchronous Write Select
. This signal is used to interface the ADSP-2106x to synchronous memory
devices (including other ADSP-21061s). The ADSP-21061 asserts
SW
(low) to provide an early indica-
tion of an impending write cycle, which can be aborted if
WR
is not later asserted (e.g. in a conditional
write instruction). In a multiprocessor system,
SW
is output by the bus master and is input by all other
ADSP-21061s to determine if the multiprocessor memory access is a read or write.
SW
is asserted at the
same time as the address output. A host processor using synchronous writes must assert this pin when
writing to the ADSP-21061(s).
Memory Acknowledge
. External devices can deassert ACK (low) to add wait states to an external
memory access. ACK is used by I/O devices, memory controllers or other peripherals to hold off
completion of an external memory access. The ADSP-21061 deasserts ACK as an output to add
wait states to a synchronous access of its internal memory. In a multiprocessor system, a slave
ADSP-21061 deasserts the bus master’s ACK input to add wait state(s) to an access of its internal
memory. The bus master has a keeper latch on its ACK pin that maintains the input at the level it
was last driven to.
DATA
47-0
I/O/T
MS
3-0
O/T
RD
I/O/T
WR
I/O/T
PAGE
O/T
ADRCLK
O/T
SW
I/O/T
ACK
I/O/S
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADSP-21061LKB-160 | ADSP-2106x SHARC DSP Microcomputer Family |
| ADSP-21061LKB-176 | ADSP-2106x SHARC DSP Microcomputer Family |
| ADSP-21061LKS-160 | ADSP-2106x SHARC DSP Microcomputer Family |
| ADSP-21061LKS-176 | ADSP-2106x SHARC DSP Microcomputer Family |
| ADSP-21062CS-160 | ADSP-2106x SHARC DSP Microcomputer Family |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-21061KS-200X | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Digital Signal Processor |
| ADSP-21061KSZ-133 | 功能描述:IC DSP CONTROLLER 32BIT 240MQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21061KSZ-160 | 功能描述:IC DSP CONTROLLER 1MBIT 240MQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-21061KSZ-200 | 功能描述:IC DSP CONTROLLER 32BIT 240MQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-21061L | 制造商:Analog Devices 功能描述: |
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