參數(shù)資料
型號： ADSP-21061KS-200
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號處理
英文描述： ADSP-2106x SHARC DSP Microcomputer Family
中文描述： 48-BIT, 50 MHz, OTHER DSP, PQFP240
封裝： MQFP-240
文件頁數(shù)： 14/47頁
文件大?。?/td> 367K
代理商： ADSP-21061KS-200
REV. B
–14–
ADSP-21061/ADSP-21061L
ADSP-21061–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS (5 V)
K Grade
Parameter
Test Conditions
Min
Max
Unit
V
DD
T
CASE
V
IH1
V
IH2
V
IL
Supply Voltage
Case Operating Temperature
High Level Input Voltage
1
High Level Input Voltage
2
Low Level Input Voltage
1, 2
4.75
0
2.0
2.2
–0.5
5.25
+85
V
DD
+ 0.5
V
DD
+ 0.5
0.8
V
°
C
V
V
V
@ V
DD
= max
@ V
DD
= max
@ V
DD
= min
NOTES
Applies to input and bidirectional pins: DATA
, ADDR
,
RD
,
WR
,
SW
, ACK,
SBTS
,
IRQ
, FLAG
3-0
,
HBG
,
CS
,
DMAR1
,
DMAR2
,
BR
, ID
, RPBA,
CPA
, TFS0, TFS1, RFS0, RFS1, LxDAT
, LxCLK, LxACK, EBOOT, LBOOT,
BMS
, TMS, TDI, TCK,
HBR
, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1.
2
Applies to input pins: CLKIN,
RESET
,
TRST
.
ELECTRICAL CHARACTERISTICS (5 V)
Parameter
Test Conditions
Min
Max
Unit
V
OH
V
OL
I
IH
I
IL
I
ILP
I
OZH
I
OZL
I
OZHP
I
OZLC
I
OZLA
I
OZLAR
I
OZLS
C
IN
High Level Output Voltage
1
Low Level Output Voltage
1
High Level Input Current
3, 4
Low Level Input Current
3
Low Level Input Current
4
Three-State Leakage Current
5, 6, 7, 8
Three-State Leakage Current
5, 9
Three-State Leakage Current
9
Three-State Leakage Current
7
Three-State Leakage Current
10
Three-State Leakage Current
8
Three-State Leakage Current
6
Input Capacitance
11, 12
@ V
DD
= min, I
OH
= –2.0 mA
2
@ V
DD
= min, I
OL
= 4.0 mA
2
@ V
DD
= max, V
IN
= V
DD
max
@ V
DD
= max, V
IN
= 0 V
@ V
DD
= max, V
IN
= 0 V
@ V
DD
= max, V
IN
= V
DD
max
@ V
DD
= max, V
IN
= 0 V
@ V
DD
= max, V
IN
= V
DD
max
@ V
DD
= max, V
IN
= 0 V
@ V
DD
= max, V
IN
= 1.5 V
@ V
DD
= max, V
IN
= 0 V
@ V
DD
= max, V
IN
= 0 V
f
IN
= 1 MHz, T
CASE
= 25
°
C, V
IN
= 2.5 V
4.1
V
V
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
mA
μ
A
mA
μ
A
pF
0.4
10
10
150
10
10
350
1.5
350
4.2
150
4.7
NOTES
1
Applies to output and bidirectional pins: DATA
47-0
, ADDR
31-0
,
MS
3-0
,
RD
,
WR
, PAGE, ADRCLK,
SW
, ACK, FLAG
3-0
, TIMEXP,
HBG
, REDY,
DMAG1
,
DMAG2
,
BR
6-1
,
CPA
, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT
3-0
, LxCLK, LxACK,
BMS
, TDO,
EMU
, ICSA.
1
2
See Output Drive Currents section for typical drive current capabilities.
1
3
Applies to input pins: ACK
SBTS
,
IRQ
2-0
,
HBR
,
CS
,
DMAR1
,
DMAR2
, ID
2-0
, RPBA, EBOOT, LBOOT, CLKIN,
RESET
, TCK. Note that ACK is pulled up
internally with 2 k
during reset in a multiprocessor system, when ID2–0 = 001 and another ADSP-2106x is not requesting bus mastership.)
1
4
Applies to input pins with internal pull-ups: DR0, DR1,
TRST
, TMS, TDI.
1
5
Applies to three-statable pins: DATA
47-0
, ADDR
31-0
,
MS
3-0
,
RD
,
WR
, PAGE, ADRCLK,
SW
, ACK, FLAG
3-0
, REDY,
HBG
,
DMAG1
,
DMAG2
,
BMS
,
BR
6–1
,
TFS
X
, RFS
X
, TDO,
EMU
. (Note that ACK is pulled up internally with 2 k
during reset in a multiprocessor system, when ID
2-0
= 001 and another ADSP-2106x is
not requesting bus mastership.)
1
6
Applies to three-statable pins with internal pull-ups: DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1.
1
7
Applies to
CPA
pin.
1
8
Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 k
during reset in a multiprocessor system, when ID
2-0
= 001 and another
ADSP-21061x is not requesting bus mastership).
1
9
Applies to three-statable pins with internal pull-downs: LxDAT
3-0
, LxCLK, LxACK.
10
Applies to ACK pin when keeper latch enabled.
11
Applies to all signal pins.
12
Guaranteed but not tested.
Specifications subject to change without notice.
相關(guān)PDF資料
PDF描述
ADSP-21061LKB-160 ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21061LKB-176 ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21061LKS-160 ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21061LKS-176 ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21062CS-160 ADSP-2106x SHARC DSP Microcomputer Family
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADSP-21061KS-200X 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Digital Signal Processor
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ADSP-21061L 制造商:Analog Devices 功能描述:
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