參數(shù)資料
型號： ADS5444_07
廠商： Texas Instruments, Inc.
英文描述： 13-BIT 250 MSPS ANALOG-TO-DIGITAL CONVERTER
中文描述： 13位250 MSPS的模擬數(shù)字轉(zhuǎn)換器
文件頁數(shù)： 6/27頁
文件大?。?/td> 1031K
代理商： ADS5444_07
www.ti.com
TIMING CHARACTERISTICS
N
N+1
N+2
N+3
N+4
N
N1
N2
N3
t
A
t
su_c
t
h_c
t
h_DR
N + 1
N
N + 2
N + 3
N + 4
t
C_DR
t
CLK
t
CLKL
CLK, CLK
D[12:0],
OVR, OVR
DRY, DRY
AIN
t
CLKH
t
DR
t
su_DR
T0073-01
t
r
t
f
TIMING CHARACTERISTICS
Min, Typ, Max over full temperature range, 50% clock duty cycle, sampling rate = 250 MSPS, AV
DD
= 5 V, DRV
DD
= 3.3 V
ADS5444
SLWS162A–AUGUST 2005–REVISED FEBRUARY 2006
Figure 1. Timing Diagram
PARAMETER
TEST CONDITIONS
MIN
TYP
500
200
MAX
UNIT
ps
fs RMS
cycles
t
A
t
J
Aperature delay
Clock slope independent aperture uncertainty (jitter)
Latency
4
Clock Input
t
CLK
t
CLKH
t
CLKL
Clock to DataReady (DRY)
t
DR
Clock rising to DataReady falling
t
C_DR
Clock rising to DataReady rising
Clock to DATA, OVR
(2)
t
r
Data rise time (20% to 80%)
t
f
Data fall time(80% to 20%)
t
su_c
Data valid to clock (setup time)
t
h_c
Clock to invalid Data (hold time)
DataReady (DRY)/DATA, OVR
(2)
t
su(DR)
Data valid to DRY
t
h(DR)
DRY to invalid Data
Clock period
Clock pulsewidth high
Clock pulsewidth low
4
2
2
ns
ns
ns
1.1
3.1
ns
ns
Clock duty cycle = 50%
(1)
2.7
3.5
0.6
0.6
3.1
0.2
ns
ns
ns
ns
1.7
0.9
2
ns
ns
1.3
(1)
(2)
t
= t
+ t
for clock duty cycles other than 50%
Data is updated with clock falling edge or DRY rising edge.
6
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相關代理商/技術參數(shù)
參數(shù)描述
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