參數(shù)資料
型號(hào)： ADS5444_07
廠商： Texas Instruments, Inc.
英文描述： 13-BIT 250 MSPS ANALOG-TO-DIGITAL CONVERTER
中文描述： 13位250 MSPS的模擬數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù)： 21/27頁(yè)
文件大?。?/td> 1031K
代理商： ADS5444_07
www.ti.com
CLK
ADS5444
CLK
0.1
μ
F
1:4
Clock
Source
MA3X71600LCTND
CLK
ADS5444
CLK
D
D
V
BB
MC100EP16DT
50
100 nF
100 nF
50
113
Q
Q
100 nF
100 nF
100 nF
499
499
Digital Outputs
The ADC provides 13 data outputs (D12 to D0, with D12 being the MSB and D0 the LSB), a data-ready signal
(DRY), and an over-range indicator (OVR) that equals a logic high when the output reaches the full-scale limits.
The output format is offset binary. It is recommended to use the DRY signal to capture the output data of the
ADS5444.
ADS5444
SLWS162A–AUGUST 2005–REVISED FEBRUARY 2006
Application Information (continued)
Figure 37. Differential Clock
Nevertheless, for jitter sensitive applications, the use of a differential clock has some advantages (as with any
other ADC) at the system level. The first advantage is that it allows for common-mode noise rejection at the PCB
level.
A differential clock also allows for the use of bigger clock amplitudes without exceeding the absolute maximum
ratings. In the case of a sinusoidal clock, this results in higher slew rates and reduces the impact of clock noise
on jitter. See Clocking High Speed Data Converters (
SLYT075
) for more details.
Figure 37
shows this approach. The back-to-back Schottky diodes can be added to limit the clock amplitude in
cases where this would exceed the absolute maximum ratings, even when using a differential clock.
Figure 38. Differential Clock Using PECL Logic
Another possibility is the use of a logic based clock, such as PECL. In this case, the slew rate of the edges will
most likely be much higher than the one obtained for the same clock amplitude based on a sinusoidal clock. This
solution would minimize the effect of the slope dependent ADC jitter. Using logic gates to square a sinusoidal
clock may not produce the best results as logic gates may not have been optimized to act as comparators,
adding too much jitter while squaring the inputs.
The common-mode voltage of the clock inputs is set internally to 2.4 V using internal 1 k
resistors. It is
recommended to use ac coupling, but if this scheme is not possible due to, for instance, asynchronous clocking,
the ADS5444 features good tolerance to clock common-mode variation.
Additionally, the internal ADC core uses both edges of the clock for the conversion process. Ideally, a 50% duty
cycle clock signal should be provided.
21
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AK135 Circular Connector; No. of Contacts:8; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:12; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:12-8 RoHS Compliant: No
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADS5444-EP 制造商:TI 制造商全稱:Texas Instruments 功能描述:13-BIT 250-MSPS ANALOG-TO-DIGITAL CONVERTER
ADS5444EVM 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 ADS5444 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V
ADS5444EVM-CVAL 制造商:Texas Instruments 功能描述:ADS5444EVM-CVAL - Boxed Product (Development Kits)
ADS5444HFGMPR 制造商:Texas Instruments 功能描述:EVAL UNIT FOR ADS5444-SP - Bulk
ADS5444IPFP 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 13 BIT 250MSPS ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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