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參數(shù)資料
| 型號： | ADS1259EVM-PDK |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 36/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT PERFORMANCE DEMO FOR ADS1259 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 14k |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 工作溫度： | -40°C ~ 125°C |
| 已用 IC / 零件： | ADS1259 |
| 已供物品： | 2 個板，文檔，軟件 |
| 其它名稱： | 296-30635 ADS1259EVM-PDK-ND |
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50W
PGA
MUX
2
3
1
4.7kW
(2)
18
19
24
1 F
m
10nF
(3)
1MW
100kW
VOP
VOCM
VON
GPIO6
GPIO5
GPIO0
12
8
DGND
VSON
DVDD
SCLK
SDO
SDI
C
S
INN2
7
INP2
10
INN1
9
INP1
VSP
+15V
(1)
+5V
+3.3V
6
17
19
15
14
11
12
13
15
14
16
13
5
(1)
VSN
-15V
(1)
11
VSOP
4
(1)
3
10
8
9
7
6
1 F
m
1 F
m
1 F
m
RESETPWDN
/
DRDY
AINP
REFOUT
AINN
SYNCOUT
START
DIN
DOUT
SCLK
CS
4
5
B
YP
AS
S
XT
AL2
XT
AL1
DGND
DVDD
A
VS
S
2
16
1
AVDD
20
VREFP
17
VREFN
18
PGA280
ADS1259
Controller
SPI
1 F
m
+
SBAS424D
– JUNE 2009 – REVISED AUGUST 2011
3. Optional readback verification of the register data
READ register command:
<20h>, <08>
The nine bytes of readback data that follow represent the nine register bytes.
4. Take the START pin high or send the START command to start conversions.
5. Optionally, send the RDATAC command
<10h>. This permits reading of conversion data without the need of
the read data command. Otherwise, the read data opcode must be sent to read each conversion result.
6. When the DRDY pin or the DRDY bit goes low, or when DOUT transitions low, read the data.
PGA280 APPLICATION
Figure 65 shows the ADS1259 connected to the PGA280. The PGA280 is a programmable gain, fully-differential
instrumentation amplifier that is ideally suited to drive the ADS1259. The amplifier features
±5V to ±18V supply
input section that accepts wide ranging signal levels and features a +5V output section that matches the
ADS1259 low-voltage inputs. The ADS1259 +2.5V REFOUT drives the PGA280 VOCM pin to level shift the
signal.
The ADS1259 provides a clock output (SYNCOUT) that drives the PGA280 (GPIO6) chopping clock input. An
optional extended CS (ECS) function feature of the PGA280 (GPIO0) allows use of one CS to alternately select
each device for SPI communication. Additionally, the optional BUFA trigger output of the PGA280 (GPIO5) starts
the ADS1259 conversions. The trigger can be delayed to occur after an input multiplexer change. The delay
allows settling of the PGA280 before the ADC conversion begins.
(1) Refer to the PGA280 product data sheet for power-supply bypassing recommendations.
(2) Locate this resistor as close as possible to pin 5 of the ADS1259.
(3) C0G or film capacitor.
Figure 65. PGA280 Driving the ADS1259
Copyright
2009–2011, Texas Instruments Incorporated
41
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS1259EVM-PDK | 制造商:Texas Instruments 功能描述:DEVELOPMENT TOOL |
| ADS1259IPW | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Low-Noise 14kSPS 24B ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1259IPW | 制造商:Texas Instruments 功能描述:A/D CONVERTER (A-D) IC |
| ADS1259IPWR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Low-Noise 14kSPS 24B ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1259QPWRQ1 | 功能描述:24 Bit Analog to Digital Converter 1 Input 1 Sigma-Delta 20-TSSOP 制造商:texas instruments 系列:- 包裝:剪切帶（CT） 零件狀態(tài):有效 位數(shù):24 采樣率（每秒）:14k 輸入數(shù):1 輸入類型:差分，單端 數(shù)據(jù)接口:SPI 配置:ADC 無線電 - S/H:ADC:- A/D 轉(zhuǎn)換器數(shù):1 架構(gòu):三角積分 參考類型:外部 電壓 - 電源，模擬:5V 電壓 - 電源，數(shù)字:2.7 V ~ 5.25 V 特性:PGA 工作溫度:-40°C ~ 105°C 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商器件封裝:20-TSSOP 標(biāo)準(zhǔn)包裝:1 |
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