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參數(shù)資料
| 型號： | ADS1259EVM-PDK |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 25/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT PERFORMANCE DEMO FOR ADS1259 |
| 標準包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 14k |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 工作溫度： | -40°C ~ 125°C |
| 已用 IC / 零件： | ADS1259 |
| 已供物品： | 2 個板，文檔，軟件 |
| 其它名稱： | 296-30635 ADS1259EVM-PDK-ND |
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1
9
17
25
33
41
DRDY
(1)
CS
(2)
SCLK
DOUT
DATAMSB
012h
(8)
DATAMID
DATALSB
CHECKSUM
(5)
DATAMSB
(6)
DIN
(7)
DataReady
NextDataReady
t
UPDATE
(3)
Hi-Z
(4)
SBAS424D
– JUNE 2009 – REVISED AUGUST 2011
Data Read Operation in Stop Continuous Mode
As shown in Figure 61, after sending the RDATA
command the data are shifted out on DOUT on the
In Stop Read Data Continuous mode, a read data
rising edges of SCLK. The MSB is clocked out on the
command (RDATA) must be sent for each new data
first rising edge of SCLK. In Gate Control mode,
read operation. New conversion data are ready when
DRDY returns to high on the first falling edge of
DRDY falls low or the DRDY register bit transitions
SCLK. In Pulse Control mode, DRDY remains low
low. The data read operation may then occur. The
until a new conversion is started.
read data command must be sent at least 20 fCLK
cycles before the DRDY falling edge or the data are
The conversion data consist of three or four bytes
incorrect. Do not the read data command during this
(MSB first), depending on whether the checksum byte
time.
is included. The data may be read multiple times by
continuing to shift the data.
(1) In Gate Control mode, DRDY returns to high on the first falling edge of SCLK. In Pulse Control mode, DRDY remains low until the next
conversion is started. The DRDY pin or DRDY register bit can also be polled to determine when data are ready.
(2) CS may be held low.
(3) tUPDATE = 20/fCLK. Do not issue the Read Data opcode during this time.
(4) During this interval, DOUT does not follow DRDY (stop continuous mode).
(5) Optional conversion data checksum.
(6) Optional repeat of previous conversion data.
(7) DIN data are latched on the falling edge of SCLK. Data are output on the rising edges of SCLK.
(8) Read Data command = 012h.
Figure 61. Data Read Operation in STOP Continuous Mode
Copyright
2009–2011, Texas Instruments Incorporated
31
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS1259EVM-PDK | 制造商:Texas Instruments 功能描述:DEVELOPMENT TOOL |
| ADS1259IPW | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Low-Noise 14kSPS 24B ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1259IPW | 制造商:Texas Instruments 功能描述:A/D CONVERTER (A-D) IC |
| ADS1259IPWR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Low-Noise 14kSPS 24B ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1259QPWRQ1 | 功能描述:24 Bit Analog to Digital Converter 1 Input 1 Sigma-Delta 20-TSSOP 制造商:texas instruments 系列:- 包裝:剪切帶（CT） 零件狀態(tài):有效 位數(shù):24 采樣率（每秒）:14k 輸入數(shù):1 輸入類型:差分，單端 數(shù)據(jù)接口:SPI 配置:ADC 無線電 - S/H:ADC:- A/D 轉(zhuǎn)換器數(shù):1 架構(gòu):三角積分 參考類型:外部 電壓 - 電源，模擬:5V 電壓 - 電源，數(shù)字:2.7 V ~ 5.25 V 特性:PGA 工作溫度:-40°C ~ 105°C 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商器件封裝:20-TSSOP 標準包裝:1 |
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