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參數(shù)資料
| 型號： | ADS1259EVM-PDK |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 22/48頁 |
| 文件大小： | 0K |
| 描述： | KIT PERFORMANCE DEMO FOR ADS1259 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 14k |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 工作溫度： | -40°C ~ 125°C |
| 已用 IC / 零件： | ADS1259 |
| 已供物品： | 2 個板，文檔，軟件 |
| 其它名稱： | 296-30635 ADS1259EVM-PDK-ND |
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+V
REF
(2
1)
-
23
-VREF
(2
1)
-
23
MSB
MID
LSB
CHECKSUM
Bit7ofChecksum
or
Flag=1;Bit0ofLSBConversionData
24-BitConversionData(CHKSUM=0)
32-BitConversionData (CHKSUM=1)
-VREF
2
23
2
1
-
23
SBAS424D
– JUNE 2009 – REVISED AUGUST 2011
DATA FORMAT
DATA CHECKSUM BYTE AND FLAG BIT
The ADS1259 outputs 24 bits of conversion data in
An optional checksum byte can be appended to the
binary twos complement format, MSB first. The data
conversion data bytes. The checksum makes the
LSB has a weight of VREF/(2
23
– 1). A positive
data word length four bytes in length instead of three.
full-scale input produces an output code of 7FFFFFh
The checksum byte is enabled by the register bit
and the negative full-scale input produces an output
CHKSUM. The checksum itself is the least significant
code of 800000h. The output clips at these codes for
byte sum of the three conversion data bytes, offset by
signals that exceed full-scale. Table 16 summarizes the
9Bh. Note that the checksum byte option only applies
ideal output codes for different input signals.
to the readback conversion data, not to register data.
The checksum is either seven bits or eight bits,
Table 16. Ideal Output Code versus Input Signal
depending if the FLAG register bit is enabled. If the
FLAG bit is enabled the checksum is seven bits, with
DIFFERENTIAL INPUT SIGNAL VIN
IDEAL OUTPUT
bit 7 replaced by the out-of-range flag. Figure 58 and
(AINP
– AINN)
Table 17 describe the combinations of the FLAG and
≥ VREF
7FFFFFh
CHKSUM register bits.
Checksum = MSB data byte + Mid data byte + LSB
000001h
data byte + 9Bh.
0
000000h
FFFFFFh
800000h
Figure 58. Checksum Byte and Out-of-Range Flag
(1) Excludes effects of noise, linearity, offset, and gain errors.
DATA INTEGRITY
Table 17. Checksum Byte and Over-Range Flag
Data readback integrity is augmented by a checksum
FLAG
CHKSUM
byte
and
redundant
data
read
capability.
The
REGISTER
checksum byte is the sum of three data conversion
BIT
DESCRIPTION
bytes, offset by 9Bh. Additionally, the data conversion
No checksum byte, no out-of-range
0
bytes may be read multiple times by continuing to
flag
shift data past the initial read of 24 bits (32 bits if
8-bit checksum byte, no
0
1
checksum is enabled).
out-of-range flag
No checksum byte, out-of-range
1
0
flag replaces LSB (bit 0) of
conversion data
7-bit checksum byte, out-of-range
1
replaces MSB (bit 7) of checksum
byte.
Copyright
2009–2011, Texas Instruments Incorporated
29
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS1259EVM-PDK | 制造商:Texas Instruments 功能描述:DEVELOPMENT TOOL |
| ADS1259IPW | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Low-Noise 14kSPS 24B ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1259IPW | 制造商:Texas Instruments 功能描述:A/D CONVERTER (A-D) IC |
| ADS1259IPWR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Low-Noise 14kSPS 24B ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1259QPWRQ1 | 功能描述:24 Bit Analog to Digital Converter 1 Input 1 Sigma-Delta 20-TSSOP 制造商:texas instruments 系列:- 包裝:剪切帶（CT） 零件狀態(tài):有效 位數(shù):24 采樣率（每秒）:14k 輸入數(shù):1 輸入類型:差分，單端 數(shù)據(jù)接口:SPI 配置:ADC 無線電 - S/H:ADC:- A/D 轉(zhuǎn)換器數(shù):1 架構(gòu):三角積分 參考類型:外部 電壓 - 電源，模擬:5V 電壓 - 電源，數(shù)字:2.7 V ~ 5.25 V 特性:PGA 工作溫度:-40°C ~ 105°C 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商器件封裝:20-TSSOP 標(biāo)準(zhǔn)包裝:1 |
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