參數(shù)資料
型號： ADP5589ACPZ-01-R7
廠商： Analog Devices Inc
文件頁數(shù)： 51/52頁
文件大小： 0K
描述： IC KEY DECODER 19I/O EXP 24LFCSP
標準包裝： 1,500
應用： 小鍵盤輸入，輸入/輸出擴展
接口： I²C
電源電壓： 1.65 V ~ 3.6 V
封裝/外殼： 24-WFQFN 裸露焊盤，CSP
供應商設備封裝： 24-LFCSP-WQ（3.5x3.5）
包裝： 帶卷 (TR)
安裝類型： 表面貼裝
ADP5589
Data Sheet
Rev. B | Page 8 of 52
DEVICE ENABLE
When sufficient voltage is applied to VDD and the RST pin is
driven with a logic high level, the ADP5589 starts up in standby
mode with all settings at default. The user can configure the
device via the I2C interface. When the RST pin is low, the
ADP5589 enters a reset state and all settings return to default.
The RST pin features a debounce filter.
DEVICE OVERVIEW
The ADP5589 contains 19 multiconfigurable input/output pins.
Each pin can be programmed to enable the device to carry out
its various functions, as follows:
Keypad matrix decoding (11-column by 8-row matrix
maximum).
General-purpose I/O expansion (up to 19 inputs/outputs).
PWM generation.
Clock division of externally supplied source.
Dual logic function building blocks (up to three inputs,
one output).
Two reset generators.
All 19 input/output pins have an I/O structure, as shown in
I/O
VDD
100k
I/O
DRIVE
DEBOUNCE
300k
09714-
005
Figure 6. I/O Structure
Each I/O can be pulled up with a 100 k or 300 k resistor or
pulled down with a 300 k resistor. For logic output drive, each
I/O has a 5 mA PMOS source and a 10 mA NMOS sink for
push-pull type output. For open-drain output situations, the
5 mA PMOS source is not enabled. For logic input applications,
each I/O can be sampled directly or, alternatively, sampled
through a debounce filter.
The I/O structure shown in Figure 6 allows for all GPI and GPO
functions, as well as PWM and clock divide functions. For key
matrix scan and decode, the scanning circuit uses the 100 k or
300 k resistor for pulling up keypad row pins and the 10 mA
NMOS sinks for grounding keypad column pins (see the Key
Scan Control section for details about key decoding).
Configuration of the device is carried out by programming an
array of internal registers via the I2C interface. Feedback of
device status and pending interrupts can be flagged to an
external processor via the INT pin.
The ADP5589 is offered with three feature sets. Table 5 lists the
options that are available for each model of the ADP5589.
Table 5. Available Options
Models
Description
ADP5589ACPZ-00-R7
ADP5589ACBZ-00-R7
All GPIOs pulled up (default option)
ADP5589ACPZ-01-R7
ADP5589ACBZ-01-R7
Reset pass-through1
ADP5589ACPZ-02-R7
ADP5589ACBZ-02-R7
Pull-down on special function pins2
1
Reset pass-through implies that the RESET1 output (R4) follows the logic
level of the reset input pin, RST, after the oscillator has been enabled.
2
Special function pins are defined as R0 (Row 0), R3 (Row 3), R4 (Row 4), C4
(Column 4), C6 (Column 6), and C9 (Column 9).
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相關代理商/技術參數(shù)
參數(shù)描述
ADP5589ACPZ-02-R7 功能描述:IC KEY DECODER 19I/O EXP 24LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產品:NXP - I2C Interface 標準包裝:1 系列:- 應用:2 通道 I²C 多路復用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1
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