參數(shù)資料
型號(hào)： ADP5589ACPZ-01-R7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 2/52頁(yè)
文件大?。?/td> 0K
描述： IC KEY DECODER 19I/O EXP 24LFCSP
標(biāo)準(zhǔn)包裝： 1,500
應(yīng)用： 小鍵盤輸入，輸入/輸出擴(kuò)展
接口： I²C
電源電壓： 1.65 V ~ 3.6 V
封裝/外殼： 24-WFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 24-LFCSP-WQ（3.5x3.5）
包裝： 帶卷 (TR)
安裝類型： 表面貼裝
ADP5589
Data Sheet
Rev. B | Page 10 of 52
KEY
SCAN
CONTROL
1
2
3
4
5
6
7
8
9
VDD
R0
R1
R2
C2
C0
C1
3 × 3 KEYPAD MATRIX
09714-
008
Figure 9. Simplified Key Scan Block
Figure 9 shows a simplified representation of the key scan block
using three row and three column pins connected to a small
3 × 3, nine-switch keypad matrix. When the key scanner is idle,
the row pins are pulled high and the column pins are driven
low. The key scanner operates by checking the row pins to see
if they are low.
If Switch 6 in the matrix is pressed, R1 connects to C2. The key
scan circuit senses that one of the row pins is pulled low, and a
key scan cycle begins. Key scanning involves driving all column
pins high, then driving each column pin, one at a time, low and
sensing whether a row pin is low or not. All row/column pairs are
scanned; therefore, if multiple keys are pressed, they are
detected.
To prevent glitches or narrow press times being registered as a
valid key press, the key scanner requires the key be pressed for
two scan cycles. The key scanner has a wait time between each
scan cycle; therefore, the key must be pressed and held for at
least this wait time to register as being pressed. If the key is
continuously pressed, the key scanner continues to scan, wait,
scan, wait, and so forth.
If Switch 6 is released, the connection between R1 and C2
breaks, and R1 is pulled up high. The key scanner requires that
the key be released for two scan cycles because the release of a
key is not necessarily in sync with the key scanner, it may take
up to two full wait/scan cycles for a key to register as released.
When the key is registered as released, and no other keys are
pressed, the key scanner returns to idle mode.
For the remainder of this document, the press/release status of a
key is represented as simply a logic signal in the figures. A logic
high level represents the key status as pressed, and a logic low
represents released. This eliminates the need to draw individual
row/column signals when describing key events.
KEY x
KEY RELEASED
KEY PRESSED
09714-
009
Figure 10. Logic Low: Released; Logic High: Pressed
Figure 11 shows a detailed representation of the key scan block
and its associated control and status signals. When all row and
column pins are used, a matrix of 88 unique keys can be
scanned.
相關(guān)PDF資料
PDF描述
V150B5H150BL CONVERTER MOD DC/DC 5V 150W
PIC16LF1509-I/SO IC MCU 8BIT 14KB FLASH 20-SOIC
VE-J44-IW-F3 CONVERTER MOD DC/DC 48V 100W
VE-J44-IW-F1 CONVERTER MOD DC/DC 48V 100W
V150B5H150B2 CONVERTER MOD DC/DC 5V 150W
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADP5589ACPZ-02-R7 功能描述:IC KEY DECODER 19I/O EXP 24LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁(yè)面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1
ADP5589CP-EVALZ 功能描述:BOARD EVAL ADP5589ACPZ RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源
ADP-5DB 制造商:Delta Power 功能描述:
ADP-5DB-A 制造商:Delta Electronics Inc 功能描述:
ADP-5DBAB 制造商:Delta Electronics Inc 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*