參數(shù)資料
型號: ADP5589ACPZ-01-R7
廠商: Analog Devices Inc
文件頁數(shù): 5/52頁
文件大?。?/td> 0K
描述: IC KEY DECODER 19I/O EXP 24LFCSP
標準包裝: 1,500
應(yīng)用: 小鍵盤輸入,輸入/輸出擴展
接口: I²C
電源電壓: 1.65 V ~ 3.6 V
封裝/外殼: 24-WFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 24-LFCSP-WQ(3.5x3.5)
包裝: 帶卷 (TR)
安裝類型: 表面貼裝
Data Sheet
ADP5589
Rev. B | Page 13 of 52
When full unlock is achieved, FIFO and event count updates
resume. Note that if a key press is used as the second unlock
event, the release of that key is captured on the FIFO after
unlocking is completed.
The ADP5589 features an unlock timer, UNLOCK_TIMER[2:0]
(0x36[2:0]). When enabled, after the first unlock event occurs,
the unlock timer begins counting, and the second unlock event
must occur before the unlock timer expires. If the unlock timer
expires, the first unlock event must occur again to restart the
unlock process. Figure 15 shows a simple state diagram of the
unlocking process.
NO
FIRST
UNLOCK
EVENT?
UNLOCK
TIMER
ENABLED?
SECOND
UNLOCK EVENT
REQUIRED?
START UNLOCK TIMER
UNLOCK
TIMER
EXPIRED?
UNLOCK
YES
NO
YES
SECOND
UNLOCK EVENT?
NO
YES
LOCKED
NO
YES
LOCK_STAT = 0
LOCK_STAT = 1
EVENT
DETECTED?
YES
NO
EVENT
DETECTED?
YES
NO
EVENT
DETECTED?
NO
09714-
014
Figure 15. State Diagram of Unlocking Process
When lock mode is enabled, no EVENT_INT interrupts can be
generated until the unlock events occur.
The ADP5589 features an interrupt mask timer, INT_MASK_
TIMER[4:0] (0x36[7:3]). When this timer and lock mode are
enabled, a single EVENT_INT is generated if any key is pressed
or any GPI (programmed to update the FIFO) is active. When
the EVENT_INT is generated, the mask timer begins counting.
No additional EVENT_INT interrupts are generated until
the mask timer expires and a new key is pressed or any GPI
(programmed to update the FIFO) is active, unless the unlock
events occur, in which case, normal operation is resumed.
Allowing a single EVENT_INT interrupt is useful to alert the
processor to turn on its screen and display an unlock message
to the user. Blanking out additional key presses ensures that the
processor is not unnecessarily interrupted until the unlock
events occur. Figure 16 shows the unlock sequence when the
interrupt mask timer is enabled.
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