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參數(shù)資料
| 型號： | ADP3204JCP-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 3-Phase IMVP-II and IMVP-III Core Controller for Mobile CPUs |
| 中文描述： | SWITCHING CONTROLLER, QCC32 |
| 封裝： | MO-220VHHD2, LFCSP-32 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 1315K |
| 代理商： | ADP3204JCP-REEL7 |
REV. 0
–6–
ADP3204
PIN FUNCTION DESCRIPTIONS
Pin
Mnemonic
Function
1–5
VID[4:0]
Voltage Identification Inputs. These are the VID inputs for logic control of the programmed
reference voltage that appears at the DACOUT pin, and, via external component configura-
tion, is used for setting the output voltage regulation point. The VID pins have a specified internal
pull-up current that, if left open, will default the pins to a logic high state. The VID code does not set
the DAC output voltage directly but through a transparent latch that is clocked by the
BOM
pin’s
GMUXSEL signal rising and falling edge.
6
BOM
Battery Optimized Mode Control (Active Low). This digital input pin corresponds to the system’s
GMUXSEL signal that corresponds to Battery Optimized Mode of the CPU operation in its active
low state and Performance Optimized Mode (POM) in its deactivated high state. The signal also
controls the optimal positioning of the core voltage regulation level by offsetting it downward in
Battery Optimized Mode according to the functionality of the BSHIFT and RAMP pins. It is also
used to initiate a masking period for the PWRGD signal whenever a GMUXSEL signal transition occurs.
7
DPSLP
Deep Sleep Mode Control (Active Low). This is a digital input pin corresponding to the system’s
STPCPU
signal that, in its active state, corresponds to Deep Sleep Mode of the CPU operation,
which is a subset operating mode of either
BOM
or POM operation. The signal controls the optimal
positioning of the core voltage regulation level by offsetting it downward according to the function-
ality of the DSHIFT and RAMP pins.
8
DPRSLP
Deeper Sleep Mode Control (Active High). This is a digital input pin corresponding to the system’s
DPRSLPVR signal corresponding to Deeper Sleep Mode of the CPU operation. When the signal
when it is activated it controls the DAC output voltage by disconnecting the VID signals from the
DAC input and setting a specified internal Deeper Sleep code instead. At de-assertion of the DPRSLPVR
signal, the DAC output voltage returns to the voltage level determined by the externalVID code.
The DPRSLPVR signal is also used to initiate a blanking period for the PWRGD signal
to disable its
response to a pending dynamic core voltage change that corresponds to the VID code transition.
9
PWRGD
Power Good (Active High). This open-drain output pin, via the assistance of an external pull-up
resistor to the desired voltage, indicates that the core voltage is within the specified tolerance
of the VID programmed value, or else is in a VID transition state as indicated by a recent state
transition of either the
BOM
or DPRSLP pins. PWRGD is deactivated (pulled low) when the IC is
disabled in UVLO mode, or starting up, or the COREFB voltage is out of the core power-good
window. The open-drain output allows external wired ANDing (logical NORing) with other open
drain/collector power-good indicators.
10
SD
Shutdown (Active Low). This is a digital input pin coming from a system signal that, in its active
state shuts down the IC operation, placing the IC in its lowest quiescent current state for maximum
power savings.
PIN CONFIGURATION
24
23
22
21
20
19
18
17
PIN 1
(Not to Scale)
VID4
VID3
VID2
VID1
VID0
BOM
DPSLP
DPRSLP
D
32 31 30 29 28 27 26 25
B
D
H
C
R
ADP3204
R
C
9 10 11 12 13 14 15 16
S
D
D
1
2
3
4
5
6
7
8
VCC
CS3
CS2
CS1
OUT3
OUT2
OUT1
GND
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相關代理商/技術參數(shù) |
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