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參數(shù)資料
| 型號： | ADP3204JCP-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 3-Phase IMVP-II and IMVP-III Core Controller for Mobile CPUs |
| 中文描述： | SWITCHING CONTROLLER, QCC32 |
| 封裝： | MO-220VHHD2, LFCSP-32 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 1315K |
| 代理商： | ADP3204JCP-REEL7 |
REV. 0
–4–
ADP3204
NOTES
1
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
2
Two test conditions: 1) PWRGD is OK but forced to fail by applying an out-of-the-Core Good-window voltage (V
COREFB, BAD
= 1.0 V at V
VID
= 1.25 V setting) to the
COREFB pin right after the moment that
BOM
or DPRSLP is asserted/de-asserted. PWRGD should not fail immediately only with the specified blanking delay
time. 2) PWRGD is forced to fail (V
COREFB, BAD
= 1.0 V at V
VID
= 1.25 V setting) but gets into the Core Good-window (V
COREFB, GOOD
= 1.25 V) right after the moment
that
BOM
or DPRSLP is asserted/de-asserted. PWRGD should not go high immediately only with the specified blanking delay time.
3
Guaranteed by design
4
Measured from 50% of VID code transition amplitude to the point where V
DACOUT
settles within
±
1% of its steady state value.
5
Measured between DACRAMP and DACOUT pins.
6
40 mVpp amplitude impulse with 20 mV overdrive. Measured from the input threshold intercept point to 50% of the output voltage swing.
7
Measured between the 30% and 70% points of the output voltage swing.
8
DPRSLP circuit meets the minimum 30 ns DPRSLPVR signal assertion requirement; guaranteed by design.
9
COREFB pin has a resistor divider to GND whose resistance is 41.3 k (typ), guaranteed by design.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
SHIFT SETTING
Battery-Shift Current
I
RAMPB
, I
CS+B
V
VID
= 1.25 V
I
BSHIFT
= –100
μ
A,
BOM
= L
DPSLP
= H
–92.5
–100
–107.5
mA
Battery-Shift Reference Voltage
V
BSHIFT
V
DAC
V
Deep Sleep-Shift Current
I
RAMPD
, I
CS+D
V
VID
= 1.25 V
I
DSHIFT
= –100
μ
A,
BOM
= H
DPSLP
= L
–92.5
–100
–107.5
mA
Deep Sleep-Shift Reference
Voltage
Deeper Sleep-Shift Current
V
DSHIFT
V
DAC
V
I
REGDPR
I
COREFBDPR8
I
DPRSHIFT
= –100
μ
A, DPRSLP = H
V
VID
= 1.25 V,
I
DPRSHIFT
= –100
μ
A,
DPRSLP = H
–90
110
–100
130
–110
150
μ
A
μ
A
Deeper Sleep-Shift Reference
Voltage
V
DPRSHIFT
V
DAC
V
SHIFT CONTROL INPUTS
BOM
Threshold
(CMOS Input)
DPSLP
Threshold
(CMOS Input)
DPRSLP Mode Threshold
8
(CMOS Input)
V
BOM
V
CC
/2
V
V
DSLP
V
CC
/2
V
V
DPRSLP
V
CC
/2
V
LOW SIDE DRIVE CONTROL
Output Voltage (CMOS Output)
V
DRVLSD
DPRSLP = H
DPRSLP = L
DPRSLP = H, V
DRVLSD
= 1.5 V
DPRSLP = L, V
DRVLSD
= 1.5 V
0
0.7 V
CC
+0.4
–0.4
0.4
V
CC
V
V
mA
mA
Output Current
I
DRVLSD
OVER/REVERSE VOLTAGE
PROTECTION CORE FEEDBACK
Overvoltage Threshold
Reverse-Voltage Threshold
Output Current
(Open-Drain Output)
V
COREFB, OVP9
V
COREFB, RVP9
I
CLAMP
V
COREFB
V
COREFB
V
COREFB
= 2.2 V, V
CLAMP
= 1.5 V
V
COREFB
= V
DAC
, V
CLAMP
= 1.5 V
2.0
–0.3
V
V
μ
A
mA
10
2
6
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