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參數(shù)資料
| 型號： | ADP3204JCP-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 3-Phase IMVP-II and IMVP-III Core Controller for Mobile CPUs |
| 中文描述： | SWITCHING CONTROLLER, QCC32 |
| 封裝： | MO-220VHHD2, LFCSP-32 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 1315K |
| 代理商： | ADP3204JCP-REEL7 |
REV. 0
ADP3204
–11–
THEORY OF OPERATION
Overview
Featuring a new proprietary 1-, 2-, or 3-channel buck converter
hysteretic control architecture developed by Analog Devices, the
ADP3204 is the optimal core voltage control solution for both
IMVP-II and IMVP-III generation microprocessors. The complex
multitiered regulation requirements of either IMVP specifica-
tion are easily implemented with the highly integrated function-
ality of this controller.
Power Conversion Control Architecture
Driving of the individual channels is accomplished using external
drivers, such as the ADP3415. One PWM interface pin per
channel, OUT1, OUT2, and OUT3, is provided. A separate
pin,
DRVLSD
, commands the driver to enable or disable synchro-
nous rectifier operation during the off time of each channel. The
same
DRVLSD
pin is connected to all three drivers.
The ADP3204 utilizes hysteretic control. The resistor from
the HYSSET pin to ground sets up a current that is switched
bidirectionally into a resistor interconnected between the RAMP
and CS+ pins. The switching of this current sets the hysteresis.
In a multichannel configuration, the hysteretic control requires
multiplexing information in all channels. The inductor current
of the channel that is driven high is controlled against the upper
hysteresis limit. During the common offtime of the channels,
the inductor currents are averaged together and compared against
the lower hysteresis limit. This proprietary offtime averaging
technique serves to eliminate a systematic offset that otherwise
appears in a fully multiplexed hysteretic control system.
Compensation
As with all ADI products for core voltage control, the controller
is compatible with ADOPT compensation, which provides the
optimum output voltage containment within a specified voltage
window or along a specified load line using the fewest possible
output capacitors. The inductor ripple current is kept at a fixed
programmable value while the output voltage is regulated with
fully programmable voltage positioning parameters, which can
be tuned to optimize the design for any particular CPU regula-
tion specification. By controlling the ripple current rather than
the ripple voltage, the frequency variations associated with
changes in output impedance for standard ripple regulators will
not appear.
Feedback/Current Sensing
Accurate current sensing is needed to accomplish output voltage
positioning accurately, which, in turn, is required to allow the
minimum number of output capacitors to be used to contain
transients. A current sense resistor is used between each inductor
and the output capacitors. To allow the control to operate
without amplifiers, the negative feedback signal is multiplexed
from the inductor or upstream side of the current sense resistors,
and a positive feedback signal, if needed for load-line tuning, is
taken from the output or downstream side.
Output Voltage Programming by VID, Offsets, and Load Line
In the IMVP-II and IMVP-III specifications, the output voltage
is a function of both the core current (according to a specified
load line) and the system operating mode (i.e., performance or
battery optimized, normal or deep sleep clocking state, or deeper
sleep). The VID code programs the “nominal” core voltage.
The core voltage decreases as a function of load current along
the load line, which is synonymous with an output resistance of
the power converter. The core voltage is also offset by a dc
value—usually specified as a percentage—depending on the
operating mode. The voltage offset is also called a “shift.”
Two pins, BSHIFT and DSHIFT, are used to program the
magnitude of the voltage shifts. The voltage shifts are accom-
plished by injecting current at the node of the negative input pin
of the feedback comparator. Resistive termination at the pins
determines the magnitude of the voltage “shifts.”
Two other pins,
BOM
and
DPSLP
, are used to activate the
respective two shifts only in their active low states. In the
ADP3204, the shifts are mutually exclusive, with the Deep
Sleep shift (controlled by the
DPSLP
and DSHIFT pins) being
the dominant one. Another pin, DPRSLP, eliminates both
shifts only in its active high state. Its assertion corresponds to
the Deeper Sleep operating mode.
Current Limiting
The current programmed at the HYSSET pin and a resistor
from the CS– pin to the common node of the current sense
resistors set the current limit. If the current limit threshold is
triggered, a hysteresis is applied to the threshold so that hysteretic
control is maintained during a current limited operating mode.
AMBIENT TEMPERATURE – C
–350
0
100
20
I
C
40
60
80
0
OUT = LOW, RHYSSET = 17k
OUT = LOW, RHYSSET = 170k
OUT = HIGH, RHYSSET = 170k
OUT = HIGH, RHYSSET = 17k
–300
–250
–200
–150
–100
–50
TPC 8. Current Limit Threshold vs. Temperature
TEMPERATURE – C
–110
0
100
20
H
40
60
80
0
110
OUT = LOW, RHYS = 17k
OUT = LOW, RHYS = 170k
OUT = HIGH, RHYS = 170k
OUT = HIGH, RHYS = 17k
TPC 7. Core Hysteresis Current vs. Temperature
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADP3205 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiphase IMVP-IV Core Controller for Mobile CPUs |
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