參數(shù)資料
型號: ADP2140ACPZ3328R7
廠商: Analog Devices Inc
文件頁數(shù): 4/32頁
文件大?。?/td> 2731K
描述: IC REG DL BCK/LINEAR 10LFCSP
標(biāo)準(zhǔn)包裝: 1
拓?fù)洌?/td> 降壓(降壓)同步(1),線性(LDO)(1)
功能: 任何功能
輸出數(shù): 2
頻率 - 開關(guān): 3MHz
電壓/電流 - 輸出 1: 3.3V,600mA
電壓/電流 - 輸出 2: 2.8V,300mA
帶 LED 驅(qū)動器:
帶監(jiān)控器:
帶序列發(fā)生器:
電源電壓: 1.65 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 10-WFDFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 10-LFCSP-WD(3x3)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: ADP2140ACPZ3328R7DKR
ADP2140
Data Sheet
 
Rev. A | Page 4 of 32
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max     Unit
Output Noise
OUT
 
V    = V    = 5 V, I     = 10 mA
 
 
 
 
 
 
10 Hz to 100 kHz, V     = 0.8 V
 
29
 
礦 rms
 
 
10 Hz to 100 kHz, V     = 1.2 V
 
40
 
礦 rms
 
 
10 Hz to 100 kHz, V
T2
 = 1.8 V
 
50
 
礦 rms
 
 
10 Hz to 100 kHz, V
T2
 = 2.5 V
 
66
 
礦 rms
 
 
10 Hz to 100 kHz, V     = 3.3 V
 
88
 
礦 rms
Current Limit
I   
T = 25癈
360
500
760
mA
Input Leakage Current
I
-
 
EN2 = GND, V    = 5.5 V and V     = 0 V
 
 
1
Start-Up Time
1
 
t
-
 
V     = 3.3 V, 300 mA load
 
70
 
Soft Start Time
2
 
SS
TIME
 
V
T2
 = 3.3 V, 300 mA load
 
130
 
ADDITIONAL FUNCTIONS
 
 
 
 
 
 
Undervoltage Lockout
UVLO
 
 
 
 
 
Input Voltage Rising
UVLO
RI E
 
 
 
2.23     2.3
V
Input Voltage Falling
UVLO
FALL
 
 
2.05
2.16     
V
EN Input
 
 
 
 
 
 
EN1, EN2 Input Logic High
V  
2.3 V d V    d 5.5 V
1.0
 
 
V
EN1, EN2 Input Logic Low
V
2.3 V d V    d 5.5 V
 
 
0.27
V
EN1, EN2 Input Leakage
I
EN-LK
 
EN1, EN2 = V
IN1
 or GND
 
0.05     
礎(chǔ)
 
 
EN1, EN2 = V
IN1
 or GND
 
 
1
礎(chǔ)
Shutdown Current
I    
V    = 5.5 V, EN1, EN2 = GND, T = 40癈 to +85癈
 
0.3
1.2
Thermal Shutdown
 
 
 
 
 
 
Threshold
TS
SD
 
T
J
 rising
 
150
 
Hysteresis
TS
SD-HYS
 
 
 
20
 
Power Good
 
 
 
 
 
 
Rising Threshold
PG   
 
 
92
 
%V   
Falling Threshold
PG    
 
 
86
 
%V   
Power-Good Hysteresis
PG   
 
 
6
 
%V   
Output Low
V
L
 
I
INK
 = 4 mA
 
 
0.2
V
Leakage Current
I  
Power-good pin pull-up voltage = 5.5 V
 
 
1
Buck to LDO Delay
t
 
PWM mode only
 
5
 
ms
Power-Good Delay
t
 
PWM mode only
 
5
 
ms
 
1
 Start-up time is defined as the time between the rising edge of ENx to V
OUTx
 being at 10% of the V
OUTx
 nominal value.
2
 Soft start time is defined as the time between V
OUTx
 being at 10% to V
OUTx
 being at 90% of the V
OUTx
 nominal value.
3
 Based on an endpoint calculation using 1 mA and 300 mA loads.
4
 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output
voltages above 2.3 V.
 
RECOMMENDED SPECIFICATIONS: CAPACITORS AND INDUCTOR
Table 2.
Parameter
Symbol
Test Conditions/Comments     Min
Typ
Max
Unit
MINIMUM INPUT AND OUTPUT CAPACITANCE
1
 
 
T
A
 = 40癈 to +125癈
 
 
 
 
Buck
C   
 
7.5
10
 
LDO
C   
 
0.7
1.0
 
CAPACITOR ESR
 
T
A
 = 40癈 to +125癈
 
 
 
?
Buck
R   
 
0.001     
0.01
?
LDO
R   
 
0.001     
1
?
MINIMUM INDUCTOR
IND   
 
0.7
1
 
 
1
 The minimum input and output capacitance should be greater than 0.70 糉 over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R- and X5R-type capacitors are recommended,
Y5V and Z5U capacitors are not recommended for use with any LDO.
 
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