參數(shù)資料
型號: ADP2140ACPZ3328R7
廠商: Analog Devices Inc
文件頁數(shù): 29/32頁
文件大?。?/td> 2731K
描述: IC REG DL BCK/LINEAR 10LFCSP
標(biāo)準(zhǔn)包裝: 1
拓?fù)洌?/td> 降壓(降壓)同步(1),線性(LDO)(1)
功能: 任何功能
輸出數(shù): 2
頻率 - 開關(guān): 3MHz
電壓/電流 - 輸出 1: 3.3V,600mA
電壓/電流 - 輸出 2: 2.8V,300mA
帶 LED 驅(qū)動器:
帶監(jiān)控器:
帶序列發(fā)生器:
電源電壓: 1.65 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 10-WFDFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 10-LFCSP-WD(3x3)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: ADP2140ACPZ3328R7DKR
Data Sheet
ADP2140
 
Rev. A | Page 29 of 32
145
135
125
115
105
95
85
75
65
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
TOTAL POWER DISSIPATION W
500mm
2
50mm
2
0mm
2
T
J MAX
 
Figure 93. Junction Temperature vs. Power Dissipation, T
A
 = 65癈
135
125
115
105
95
85
0
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
TOTAL POWER DISSIPATION W
500mm
2
50mm
2
0mm
2
T
J MAX
 
Figure 94. Junction Temperature vs. Power Dissipation, T
A
 = 85癈
In cases where the board temperature is known, use the thermal
characterization parameter, ?/DIV>
JB
, to estimate the junction temper-
ature rise. Maximum junction temperature (T
J
) is calculated
from the board temperature (T
B
) and power dissipation (P
D
)
using the formula
T
J
 = T
B
 + (P
D
 ??/DIV>
JB
)
(5)
The typical ?/DIV>
JB
 value for the 10-lead, 3 mm ?3 mm LFCSP is
16.9癈/W.
140
100
120
80
60
40
20
0
0.5    1.0    1.5    2.0    2.5    3.0    3.5    4.0    4.5    5.0
TOTAL POWER DISSIPATION W
T
B
 = 25癈
T
B
 = 50癈
T
B
 = 65癈
T
B
 = 85癈
T
J MAX
 
Figure 95. Junction Temperature vs. Power Dissipation
PCB LAYOUT CONSIDERATIONS
Improve heat dissipation from the package by increasing
the amount of copper attached to the pins of the ADP2140.
However, as listed in Table 10, a point of diminishing returns
is eventually reached, beyond which an increase in the copper
size does not yield significant heat dissipation benefits.
Poor layout can affect the ADP2140 buck performance causing
electromagnetic interference (EMI) and electromagnetic compa-
tibility (EMC) performance, ground bounce, and voltage losses;
thus, regulation and stability can be affected. Implement a good
layout using the following rules:
"     Place the inductor, input capacitor, and output capacitor
close to the IC using short tracks. These components carry
high switching frequencies and long, large tracks act like
antennas.
"     Route the output voltage path away from the inductor and
SW node to minimize noise and magnetic interference.
"     Use a ground plane with several vias connected to the
component-side ground to reduce noise interference on
sensitive circuit nodes.
"     Use of 0402- or 0603-size capacitors achieves the smallest
possible footprint solution on boards where area is limited.
 
Figure 96. PCB Layout, Top
 
Figure 97. PCB Layout, Bottom
 
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