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參數(shù)資料
| 型號(hào)： | ADP2140ACPZ3328R7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 19/32頁 |
| 文件大?。?/td> | 2731K |
| 描述： | IC REG DL BCK/LINEAR 10LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 拓?fù)洌?/td> | 降壓（降壓）同步（1），線性（LDO）（1） |
| 功能： | 任何功能 |
| 輸出數(shù)： | 2 |
| 頻率 - 開關(guān)： | 3MHz |
| 電壓/電流 - 輸出 1： | 3.3V，600mA |
| 電壓/電流 - 輸出 2： | 2.8V，300mA |
| 帶 LED 驅(qū)動(dòng)器： | 無 |
| 帶監(jiān)控器： | 無 |
| 帶序列發(fā)生器： | 是 |
| 電源電壓： | 1.65 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-WFDFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 10-LFCSP-WD（3x3） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | ADP2140ACPZ3328R7DKR |
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Data Sheet
ADP2140
Rev. A | Page 19 of 32
THEORY OF OPERATION
PWM/
PSM
CONTROL
ENABLE/
SEQUENCING
Gm ERROR
AMP
SOFT
START
REFERENCE
0.5V
3MHz
OSCILLATOR
CURRENT
LIMIT
POWER
GOOD
THERMAL
SHUTDOWN
R1
R2
FB
VIN2
GND
EN1
EN2
UVLO
VIN1
SW
PGND
PG
EPAD
CURRENT
SENSE AMP
ZERO-CROSS
COMPARATOR
FB
DRIVER
AND
ANTISHOOT
THROUGH
Figure 69. Internal Block Diagram
BUCK SECTION
The ADP2140 contains a step-down dc-to-dc converter that
uses a fixed frequency, high speed current-mode architecture. The
high 3 MHz switching frequency and tiny 10-lead, 3 mm ?3 mm
LFCSP package allow for a small step-down dc-to-dc converter
solution.
The ADP2140 operates with an input voltage from 2.3 V to 5.5 V .
Output voltage options are 1.0 V , 1.1 V , 1.2 V , 1.5 V , 1.8 V, 1.875 V ,
2.5 V, and 3.3 V.
CONTROL SCHEME
The ADP2140 operates with a fixed frequency, current-mode
PWM control architecture at medium to high loads for high
efficiency, but shifts to a variable frequency control scheme at
light loads for lower quiescent current. When operating in fixed
frequency PWM mode, the duty cycle of the integrated switches
adjust to regulate the output voltage, but when operating in power
saving mode (PSM) at light loads, the switching frequency adjusts
to regulate the output voltage.
The ADP2140 operates in the PWM mode only when the load
current is greater than the pulse skipping threshold current. At
load currents below this value, the converter smoothly transitions
to the PSM mode of operation.
PWM OPERATION
In PWM mode, the ADP2140 operates at a fixed frequency of
3 MHz set by an internal oscillator. At the start of each oscillator
cycle, the P-channel MOSFET switch is turned on, putting a
positive voltage across the inductor. Current in the inductor
increases until the current sense signal crosses the peak inductor
current level that turns off the P-channel MOSFET switch and
turns on the N-channel MOSFET synchronous rectifier. This
puts a negative voltage across the inductor, causing the inductor
current to decrease. The synchronous rectifier stays on for the
remainder of the cycle, unless the inductor current reaches zero,
which causes the zero-crossing comparator to turn off the
N-channel MOSFET.
PSM OPERATION
The ADP2140 has a smooth transition to the variable frequency
PSM mode of operation when the load current decreases below
the pulse skipping threshold current, switching only as necessary to
maintain the output voltage within regulation. When the output
voltage dips below regulation, the ADP2140 enters PWM mode
for a few oscillator cycles to increase the output voltage back to
regulation. During the wait time between bursts, both power
switches are off, and the output capacitor supplies the entire
load current. Because the output voltage occasionally dips and
recovers, the output voltage ripple in this mode is larger than the
ripple in the PWM mode of operation.
PULSE SKIPPING THRESHOLD
The output current at which the ADP2140 transitions from
variable frequency PSM control to fixed frequency PWM control
is called the pulse skipping threshold. The pulse skipping threshold
has been optimized for excellent efficiency over all load currents.
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