Table 2. I2C Timing Parameters
參數(shù)資料
型號: ADN8102ACPZ-R7
廠商: Analog Devices Inc
文件頁數(shù): 32/36頁
文件大?。?/td> 0K
描述: IC EQUALIZER 4CH XSTREAM 64LFCSP
標(biāo)準(zhǔn)包裝: 750
系列: XStream™
應(yīng)用: 以太網(wǎng)控制器
接口: I²C
電源電壓: 1.8 V ~ 3.3 V
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 帶卷 (TR)
安裝類型: 表面貼裝
ADN8102
Rev. B | Page 5 of 36
TIMING SPECIFICATIONS
Table 2. I2C Timing Parameters
Parameter
Min
Max
Unit
Description
fSCL
0
400
kHz
SCL clock frequency
tHD:STA
0.6
Not applicable
μs
Hold time for a start condition
tSU:STA
0.6
Not applicable
μs
Setup time for a repeated start condition
tLOW
1.3
Not applicable
μs
Low period of the SCL clock
tHIGH
0.6
Not applicable
μs
High period of the SCL clock
tHD:DAT
0
Not applicable
μs
Data hold time
tSU:DAT
10
Not applicable
ns
Data setup time
tR
1
300
ns
Rise time for both SDA and SCL
tF
1
300
ns
Fall time for both SDA and SCL
tSU:STO
0.6
Not applicable
μs
Setup time for a stop condition
tBUF
1
Not applicable
ns
Bus free time between a stop and a start condition
CIO
5
7
pF
Capacitance for each I/O pin
tRESET
10
Not applicable
ns
Reset pulse width1
1 Reset pulse width is defined as the time RESET is held below the logic low threshold (VIL) listed in Table 1 while the DVCC supply is within the operating range in Table 1.
07
06
0-
01
0
S
P
Sr
S
SDA
SCL
tF
tR
tF
tR
tBUF
tLOW
tHD:STA
tHD:DAT
tHIGH
tSU:DAT
tSU:STA
tSU:STO
tHD:STA
Figure 2. I2C Timing Diagram
07
06
0-
1
03
4.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
5
10
15
20
25
30
35
40
45
50
VO
L
T
A
G
E
(
V)
TIME (ns)
tRESET
DVCC (V)
DVCC MAX LIMIT
DVCC MIN LIMIT
RESET
Figure 3. Reset Timing Diagram
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