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| 型號： | ADN8102ACPZ-R7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/36頁 |
| 文件大小： | 0K |
| 描述： | IC EQUALIZER 4CH XSTREAM 64LFCSP |
| 標準包裝： | 750 |
| 系列： | XStream™ |
| 應用： | 以太網(wǎng)控制器 |
| 接口： | I²C |
| 電源電壓： | 1.8 V ~ 3.3 V |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
| 安裝類型： | 表面貼裝 |
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ADN8102
Rev. B | Page 24 of 36
SELECTIVE SQUELCH AND DISABLE
Each transmitter is equipped with output disable and output
squelch controls. Disable is a full power-down state: the trans-
mitter current is reduced to zero, and the output pins pull up
to VTTO, but there is a delay of approximately 1 μs associated
with re-enabling the transmitter. The output disable control is
accessed through the EN bit (Bit 4) of the OUT_A/OUT_B
configuration registers through the I2C control interface.
Squelch is not a full power-down state but a state in which only
the output current is reduced to zero and the output pins pull
up to VTTO, and there is a much smaller delay to bring back the
output current. The output squelch and the output disable control
can both be accessed through the OUT_A/OUT_B squelch
control registers, with the top nibble representing the squelch
control for one entire output port, and the bottom nibble
representing the output disable for one entire output port. The
ports are disabled or squelched by writing 0s to the corresponding
nibbles. The ports are enabled by writing all 1s, which is the
default setting. For example, to squelch Port A, Register 0xC3
must be set to 0x0F. The entire nibble must be written to all 0s
for this functionality.
Table 18. Squelch and Disable Control Registers
Name
Address
Data
Default
OUT_A/
OUT_B
squelch
control
0xC3,
0xE3
SQUELCH[3:0]
DISABLE[3:0]
0xFF
Table 19. Squelch and Disable Functionality
SQUELCH[3:0]
DISABLE[3:0]
Output State
1111
Enabled (default)
xxxx1
Disabled
0000
1111
Squelched
1 xxxx = don’t care
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