參數(shù)資料
型號： ADN8102ACPZ-R7
廠商： Analog Devices Inc
文件頁數(shù)： 20/36頁
文件大?。?/td> 0K
描述： IC EQUALIZER 4CH XSTREAM 64LFCSP
標準包裝： 750
系列： XStream™
應(yīng)用： 以太網(wǎng)控制器
接口： I²C
電源電壓： 1.8 V ~ 3.3 V
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
安裝類型： 表面貼裝
ADN8102
Rev. B | Page 27 of 36
APPLICATIONS INFORMATION
OUTPUT COMPLIANCE
In low voltage applications, users must pay careful attention
to both the differential and common-mode signal levels. The
choice of output voltage swing, preemphasis setting, supply
voltages (VCC and VTTO), and output coupling (ac or dc) affect
peak and settled single-ended voltage swings and the common-
mode shift measured across the output termination resistors.
These choices also affect output current and, consequently,
power consumption. For ac-coupled applications, certain
combinations of supply voltage, output voltage swing, and
preemphasis settings may violate the single-ended absolute output
low voltage, as specified in Table 1. Under these conditions,
the performance is degraded; therefore, these settings are not
recommended. Table 21 includes annotations that identify these
settings. In dc-coupled applications, the far-end termination voltage
should be equal to VTTO to allow the full list of output swing and
preemphasis settings listed in Table 17.
TxHeadroom
The TxHeadroom register (Register 0x23) allows configuration
of the individual transmitters for extra headroom at the output
for high current applications. The bits in this register are active
high (default) and are one per output (see Table 22). Setting a
bit high puts the respective transmitter in a configuration for
extra headroom, and setting a bit low does not provide extra
headroom. The TxHeadroom bits should only be set high when
required for a given output swing as listed in Table 21. Note that
TxHeadroom is not available for VCC < 2.5 V.
VH-DC
VH-PE
VSW-PE
VL-PE
VL-DC
tPE
VTTO
VOCM
VSW-DC
0
706
0-
1
40
Figure 44. Simplified Output Voltage Levels Diagram
Table 20. Symbol Definitions
Symbol
Formula
Definition
IDC
Programmable
Output current that sets output level
IPE
Programmable
Output current for PE delayed tap
ITTO
IDC + IPE
Total transmitter output current
VDPP-DC
25 Ω × IDC × 2
Peak-to-peak differential voltage swing of
nonpreemphasized waveform
VDPP-PE
25 Ω × ITTO × 2
Peak-to-peak differential voltage swing of preemphasized
waveform
VSW-DC
VDPP-DC/2 = VH-DC – VL-DC
DC single-ended voltage swing
VSW-PE
VDPP-PE/2 = VH-PE – VL-PE
Preemphasized single-ended voltage swing
VOCM_DC-COUPLED
25 Ω × ITTO/2
Output common-mode shift, dc-coupled outputs
VOCM_AC-COUPLED
50 Ω × ITTO/2
Output common-mode shift, ac-coupled outputs
VOCM
VTTO VOCM = ( VH-DC + VL-DC )/2
Output common-mode voltage
VH-DC
VTTO VOCM + VDPP-DC/2
DC single-ended output high voltage
VL-DC
VTTO VOCM VDPP-DC/2
DC single-ended output low voltage
VH-PE
VTTO VOCM + VDPP-PE/2
Maximum single-ended output voltage
VL-PE
VTTO VOCM VDPP-PE/2
Minimum single-ended output voltage
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