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| 型號： | ADN8102ACPZ-R7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 19/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC EQUALIZER 4CH XSTREAM 64LFCSP |
| 標準包裝： | 750 |
| 系列： | XStream™ |
| 應用： | 以太網(wǎng)控制器 |
| 接口： | I²C |
| 電源電壓： | 1.8 V ~ 3.3 V |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
| 安裝類型： | 表面貼裝 |
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ADN8102
Rev. B | Page 26 of 36
I2C INTERFACE DATA TRANSFERS—DATA READ
To read data from the ADN8102 register set, a microcontroller,
or any other I2C master, needs to send the appropriate control
signals to the ADN8102 slave device. The steps that need to be
completed are listed as follows, where the signals are controlled
by the I2C master, unless otherwise specified. A diagram of the
procedure can be seen in Figure 43.
1.
Send a start condition (while holding the SCL line high,
pull the SDA line low).
2.
Send the ADN8102 part address (seven bits) whose
upper five bits are the static value 10010b and whose
lower two bits are controlled by the input pins ADDR[1:0].
This transfer should be MSB first.
3.
Send the write indicator bit (0).
4.
Wait for the ADN8102 to acknowledge the request.
5.
Send the register address (eight bits) from which data is
to be read. This transfer should be MSB first. The register
address is kept in memory in the ADN8102 until the
part is reset or the register address is written over with
the same procedure (Step 1 to Step 6).
6.
Wait for the ADN8102 to acknowledge the request.
7.
Send a repeated start condition (while holding the SCL
line high, pull the SDA line low).
8.
Send the ADN8102 part address (seven bits) whose
upper five bits are the static value 10010b and whose
lower two bits are controlled by the input pins ADDR[1:0].
This transfer should be MSB first.
9.
Send the read indicator bit (1).
10.
Wait for the ADN8102 to acknowledge the request.
11.
The ADN8102 then serially transfers the data (eight bits)
held in the register indicated by the address set in Step 5.
12.
Acknowledge the data.
13a.
Send a stop condition (while holding the SCL line high,
pull the SDA line high) and release control of the bus.
13b.
Send a repeated start condition (while holding the SCL
line high, pull the SDA line low) and continue with Step 2
of the write procedure (in the I2C Interface Data
Transfers—Data Write section) to perform a write.
13c.
Send a repeated start condition (while holding the SCL
line high, pull the SDA line low) and continue with Step 2 of
this procedure to perform a read from a another address.
13d.
Send a repeated start condition (while holding the SCL
line high, pull the SDA line low) and continue with Step 8 of
this procedure to perform a read from the same address.
Figure 43 shows the ADN8102 read process. The SCL signal is
shown along with a general read operation and a specific example.
In the example, Data 0x49 is read from Address 0x6D of an
ADN8102 part with a part address of 0x4B. The part address is
seven bits wide. The upper five bits of the ADN8102 are internally
set to 10010b. The lower two bits are controlled by the ADDR[1:0]
pins. In this example, the bits controlled by the ADDR[1:0] pins
are set to 11b. In Figure 43, the corresponding step number is
visible in the circle under the waveform. The SCL line is driven
by the I2C master and never by the ADN8102 slave. As for the SDA
line, the data in the shaded polygons is driven by the ADN8102,
whereas the data in the nonshaded polygons is driven by the I2C
master. The end phase case shown is that of Step 13a.
Note that the SDA line changes only when the SCL line is low,
except for the case of sending a start, stop, or repeated start
condition, as in Step 1, Step 7, and Step 13. In Figure 43, A is the
same as ACK in Figure 42. Equally, Sr represents a repeated
start where the SDA line is brought high before SCL is raised.
SDA is then dropped while SCL is still high.
3
2
1
SCL
SDA
GENERAL CASE
EXAMPLE
4
5
6
7
8
10
9
8
11
12
13a
07
06
0-
00
9
START
REGISTER ADDR
AA
ASr
A
STOP
DATA
FIXED PART
ADDR
FIXED PART
ADDR
[1:0]
ADDR
[1:0]
R/
W
R/
W
Figure 43. I2C Read Diagram
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