參數(shù)資料
型號(hào)： ADN4604ASVZ-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 28/40頁(yè)
文件大?。?/td> 0K
描述： IC CROSSPOINT SWIT 16X16 100TQFP
標(biāo)準(zhǔn)包裝： 1,000
系列： XStream™
功能： 交叉點(diǎn)開關(guān)
電路： 1 x 16:16
電壓電源： 單電源
電壓 - 電源，單路/雙路(±)： 2.7 V ~ 3.6 V
電流 - 電源： 95mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 帶卷 (TR)
ADN4604
Data Sheet
Rev. A | Page 34 of 40
SUPPLY SEQUENCING
Ideally, all power supplies should be brought up to the appropri-
ate levels simultaneously (power supply requirements are set by
the supply limits in Table 1 and the absolute maximum ratings
listed in Table 4). If the power supplies to the ADN4604 are
brought up separately, the supply power-up sequence is as follows:
DVCC powered first, followed by VCC, and, last the termination
supplies (VTTIE, VTTIW, VTTON, and VTTOS). The power-down
sequence is reversed with termination supplies being powered
off first. The termination supplies contain ESD protection
diodes to the VCC power domain. To avoid a sustained high
current condition in these devices (ISUSTAINED < 100 mA), the
VTTI and VTTO supplies should be powered on after VCC and
should be powered off before VCC.
If the system power supplies have a high impedance in the
powered off state, then supply sequencing is not required
provided the following limits are observed:
Peak current from VTTIx or VTTOx to VCC < 200 mA
Sustained current from VTTIx or VTTOx to VCC < 100 mA
POWER DISSIPATION
The power dissipation of the ADN4604 depends on the supply
voltages, I/O coupling type, and device configuration. The
input termination resistors dissipate power depending on the
differential input swing and common-mode voltage. When ac-
coupled, the common-mode voltage is equal to the termination
supply voltage (VTTIE or VTTIW). While the current drawn from
the input termination supply is effectively zero, there is still
power and heat dissipated in the termination resistors as a result
of the differential signal swing. The core supply current and
output termination current are strongly dependent on device
configuration, such as the number of channels enabled, output
level setting, and output preemphasis setting.
In high ambient temperature operating conditions, it is impor-
tant to avoid exceeding the maximum junction temperature of
the device. Limiting the total power dissipation can be achieved
by the following:
Reducing the output swing
Reducing the preemphasis level
Decreasing the supply voltages within the allowable ranges
defined in Table 1
Disabling unused channels
Alternatively, the thermal resistance can be reduced by
Adding an external heat-sink
Increasing the airflow
section for recommendations for proper thermal stencil layout
and fabrication.
OUTPUT COMPLIANCE
In low voltage applications, users must pay careful attention
to both the differential and common-mode signal level. The
choice of output voltage swing, preemphasis setting, supply
voltages (VCC and VTTO), and output coupling (ac or dc) affect
peak and settled single-ended voltage swings and the common-
mode shift measured across the output termination resistors.
These choices also affect output current and, consequently,
power consumption. Table 19 shows the change in output
common mode (ΔVOCM = VCC VOCM) with output level and
preemphasis setting. Single-ended output levels are calculated
for VTTO supplies of 3.3 V and 2.5 V to illustrate practical
challenges of reducing the supply voltage. The minimum VL (min
VL) cannot be below the absolute minimum level specified in
Table 1. The combinations of output level, preemphasis, supply
voltage, and output coupling for which the minimum VL
specification is violated are listed as N/A in Table 1.
Since the absolute minimum output voltage specified in Table 1
is relative to VCC, decreasing VCC is required to maintain the
output levels within the specified limits when lower output
termination voltages are required. VTTO voltages as low as 1.8 V
are allowable for output swings less than or equal to 400 mV
(single-ended). Figure 54 illustrates an application where the
ADN4604 is used as a dc-coupled level translator to interface a
3.3 V CML driver to an ASIC with 1.8 V I/Os. The diode in
series with VCC reduces the voltage at VCC for improved output
compliance.
CML
VEE
VTTOx
1.8V
3.3V
VCC
VTTIx
ADN4604
CML
3.3V
Z0
07934-
054
ASIC
Rx
Figure 54. DC-Coupled Level Translator Application Circuit
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