參數(shù)資料
型號(hào)： ADN4604ASVZ-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 13/40頁(yè)
文件大?。?/td> 0K
描述： IC CROSSPOINT SWIT 16X16 100TQFP
標(biāo)準(zhǔn)包裝： 1,000
系列： XStream™
功能： 交叉點(diǎn)開(kāi)關(guān)
電路： 1 x 16:16
電壓電源： 單電源
電壓 - 電源，單路/雙路(±)： 2.7 V ~ 3.6 V
電流 - 電源： 95mA
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 帶卷 (TR)
ADN4604
Data Sheet
Rev. A | Page 20 of 40
Table 11 displays the TX Basic Control register. The TX Basic Control register consists of one byte (8 bits) for each of the 16 output
channels. Each TX Basic Control register has the same functionality. The mapping of register address to output channel is shown in the
first column. All outputs can be simultaneously programmed with a common output level, pre-emphasis and enable state using the TX
broadcast register at Address 0x18 as shown in Table 11. Note that this overwrites any data previously stored in Addresses 0x20 to 0x2F.
This register only affects the state of the TX Basic Control Register and not the TX Lookup Table, TX Advanced Control, nor XPT
Control registers.
Table 11. TX Basic Control Register
Address: Channel
Default
Register Name
Bit
Bit Name
Description
0x18: Broadcast1,
0x20: Output 0,
0x21: Output 1,
0x22: Output 2,
0x23: Output 3,
0x24: Output 4,
0x25: Output 5,
0x26: Output 6,
0x27: Output 7,
0x28: Output 8,
0x29: Output 9,
0x2A: Output 10,
0x2B: Output 11,
0x2C: Output 12,
0x2D: Output 13,
0x2E: Output 14,
0x2F: Output 15
0x00
TX basic control
6
TX CTL SELECT
0: PE and output level control is derived from
common lookup table
1: PE and output level control is derived from per port
drive control registers
5:4
TX EN[1:0]
00: TX disabled, lowest power state
01: TX standby.
10: TX squelched.
11: TX enabled
3
Reserved
Reserved. Set to 0.
2:0
PE[2:0]
If TX CTL SELECT = 0, see Table 10
000: Table Entry 0
001: Table Entry 1
010: Table Entry 2
011: Table Entry 3
100: Table Entry 4
101: Table Entry 5
110: Table Entry 6
111: Table Entry 7
If TX CTL SELECT = 1, PE[2:0] are ignored
1 The broadcast register, Address 0x18, is write-only.
Table 12 displays the TX lookup table register. The TX lookup table register consists of two bytes (16 bits) for each of the eight possible
table entries selected by the PE[2:0] field in Table 11. The mapping of table entry to register address is shown in the first column. By
default, the TX Lookup Table register contains the preemphasis settings listed in Table 10, however, these values can be changed for a
flexible selection of output levels and preemphasis boosts. Table 13 lists a variety of possible output level and preemphasis boost settings
and the corresponding TX Drive 0 and TX Drive 1 codes.
Table 12. TX Lookup Table Registers
Address: Channel
Default
Register Name
Bit
Bit Name
Description
0x60: Table Entry 0
0xFF
TX Lookup
Table Drive 0
7
DRV EN1
0: Driver 1 disabled
1: Driver 1 enabled
0x62: Table Entry 1
0xFF
0x64: Table Entry 2
0xFF
6:4
DRV LV1[2:0]
Driver 1 current = decimal(DRV LV1[2:0]) + 1
0x66: Table Entry 3
0xFF
0x68: Table Entry 4
0xDC
3
DRV EN0
0: Driver 0 disabled
1: Driver 0 enabled
0x6A: Table Entry 5
0xBB
0x6C: Table Entry 6
0x99
2:0
DRV LV0[2:0]
Driver 0 current = decimal(DRV LV0[2:0]) + 1
0x6E: Table Entry 7
0x99
0x61: Table Entry 0
0x00
TX Lookup
Table Drive 1
7
DRV END
0: Driver D disabled
1: Driver D enabled
0x63: Table Entry 1
0x99
0x65: Table Entry 2
0xCC
6:4
DRV LVD[2:0]
Driver D Current = decimal(DRV LVD[2:0]) + 1
0x67: Table Entry 3
0xFF
0x69: Table Entry 4
0xFF
3
DRV EN2
0: Driver 2 disabled
1: Driver 2 enabled
0x6B: Table Entry 5
0xFF
0x6D: Table Entry 6
0xDD
2:0
DRV LV2[2:0]
Driver 2 current = decimal(DRV LV2[2:0]) + 1
0x6F: Table Entry 7
0xDD
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