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參數(shù)資料
| 型號： | ADMC330BST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Single Chip DSP Motor Controller |
| 中文描述： | 0-BIT, 20 MHz, OTHER DSP, PQFP80 |
| 封裝： | PLASTIC, TQFP-80 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大小： | 163K |
| 代理商： | ADMC330BST |
ADMC330
–5–
REV. 0
T he ADMC330 operates with a 50 ns instruction cycle time.
Every instruction can execute in a single processor cycle.
T he flexible architecture and comprehensive instruction set of
the ADMC330 allow the processor to perform multiple opera-
tions in parallel. In one processor cycle the ADMC330 can:
generate the next program address
fetch the next instruction
perform one or two data moves
update one or two data address pointers
perform a computational operation
T his takes place while the processor continues to:
receive and transmit data through the two serial ports
decrement the timer
Independently the peripheral blocks can:
generate three-phase PWM waveforms for a power inverter
generate two signals using the 8-bit auxiliary PWM timers
acquire four analog signals
control eight digital I/O lines
decrement the watchdog timer
ROM Code Functions
T he ADMC330 has a 2K Boot ROM that contains the
following:
Monitor Program:
Serial Boot Loader for OT P ROM or EEPROM
UART Debugger Interface and Loader
Math Utilities/T ables:
Sine, cosine, tangent, inverse tangent, log, inverse log,
square root, 1/X , 1/(sine rms), unsigned division, Cartesian
to polar conversion, interpolation
T he ADMC330 is similar to an ADSP-2172 in its booting se-
quence. T he MMAP and BMODE pins are tied high, which
enables the on-chip ROM and starts execution of the monitor
program on power-up or reset. T he monitor program first at-
tempts to boot load through SPORT 1 from a serial memory
device. T he loader uses a two-wire (data and clock) serial proto-
col. T he ADMC330 provides a serial clock to the device equal
to 1/20 of CLK OUT . Default input is from a X ilinx X C1765D
OT P ROM or Atmel AT 17C65 EEPROM; other devices are
possible as long as they adhere to the loader protocol. If the
serial load is successful, the code that was downloaded is ex-
ecuted at the start of user memory space.
Failing a synchronous boot load, the ADMC330 monitor switches
over to debug mode and waits for commands over SPORT 1
from a UART . Debug mode uses a standard RS-232 protocol in
which only the data receive and transmit lines are used by the
ADMC330. T his interface is used by the Visual DSP
Debugger,
but can also be used by UART devices for boot loading programs.
In addition to the monitor program, the ROM contains the
previously listed math utilities. T hese routines can be called
from user applications.
Development System
T he ADSP-2100 Family Development Software, a complete set
of tools for software and hardware system development, sup-
ports the ADMC330. T he system builder provides a high level
method for defining the architecture of systems under develop-
ment. T he assembler has an algebraic syntax that is easy to
program and debug. T he linker combines object files into
an executable file. T he simulator provides an interactive
instruction-level simulation with a reconfigurable user interface
to display different portions of the hardware environment. A
MAK EPROM utility splitter generates PROM programmer
compatible files. T he C Compiler, based on the Free Software
Foundation’s GNU C Compiler, generates ADMC330 assem-
bly source code. T he runtime library includes over 100 ANSI-
standard mathematical and DSP-specific functions.
Low cost, easy-to-use hardware development tools include an
ADMC330-EVAL board and a windows based software debugger.
T his debugger can be run with either the ADMC330-EVAL
board or the target system by communicating over a two-wire
asynchronous link to a PC.
FUNCT IONAL DE SCRIPT ION
ADMC330 Peripherals Overview
T he ADMC330 set of peripherals was specifically developed to
address the requirements of variable speed control of ac induc-
tion motors (ACIM) and electronically commutated synchro-
nous motors (ECM). T hey are memory mapped to a block in
the DSP data memory space allowing single cycle read and/or
write to all peripheral registers. T he operation of the peripherals
is synchronized to the DSP core by a clock HCLK , which is
derived from half of the DSP system clock.
T hree-Phase PWM Generator
12-bit center-based PWM generator including program-
mable deadtime and narrow pulse deletion.
ECM crossover block.
Output enable block.
Hardwired output polarity control.
External trip input.
Pulsed PWM output capability for transformer coupled gate.
Analog I/O
T wo 8-bit PWM Output T imers—(Synthesized Analog
Output).
Comparator based Analog Input Acquisition. Analog-to-digital
conversion is accomplished via 4-channel single slope ADC.
Digital I/O
Eight bits of programmable digital I/O configurable as
interrupt sources.
T HRE E -PHASE PWM GE NE RAT OR
T he ADMC330 PWM controller is a self-contained program-
mable waveform generator that produces PWM switching sig-
nals for a three-phase power inverter. It includes a waveform
timing edge calculation unit which allows the generation of six
center based PWM signals based on only three duty cycle regis-
ter updates every switching cycle. T his minimizes the DSP
software required to service the PWM controller and frees up
processor time for the motor control law implementation. In the
default configuration it produces the three-phase center based
PWM waveforms required for three phase sinusoidal inverter.
However, it can also be configured for space vector modulation
schemes, or for controlling brushless dc motors (sometimes
known as electronically commutated motors). It also has func-
tions which simplify the interface to the power inverter gate
drive and protection circuits.
T he PWM controller is synchronized to the DSP core by the
HCLK which runs at half the DSP clock frequency giving wave-
form resolution of 100 ns with a 20 MHz DSP clock. T here are
Visual DSP is a registered trademark of Analog Devices, Inc.
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