參數(shù)資料
型號(hào)： ADMC330BST
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： Single Chip DSP Motor Controller
中文描述： 0-BIT, 20 MHz, OTHER DSP, PQFP80
封裝： PLASTIC, TQFP-80
文件頁(yè)數(shù)： 12/20頁(yè)
文件大?。?/td> 163K
代理商： ADMC330BST
ADMC330
–12–
REV. 0
OUTPUT REGS
INPUT REGS
OUTPUT REGS
INPUT REGS
OUTPUT REGS
INPUT REGS
DATA
ADDRESS
GENERATOR
#1
DATA
ADDRESS
GENERATOR
#2
INSTRUCTION
REGISTER
PROGRAM
SEQUENCER
PROGRAM ROM
2K
3
24
PROGRAM SRAM
2K
3
24
DATA
SRAM
1K
3
16
FLAGS
PMA BUS
DMA BUS
PMD BUS
DMD BUS
14
14
24
16
BUS
EXCHANGE
COMPANDING
CIRCUITRY
CONTROL
LOGIC
TIMER
TRANSMIT REG
RECEIVE REG
SERIAL
PORT 1
TRANSMIT REG
RECEIVE REG
SERIAL
PORT 0
5
5
16
R BUS
ALU
MAC
SHIFTER
Figure 9. DSP Core Block Diagram
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these compu-
tational units. T he sequencer supports conditional jumps, sub-
routine calls and returns in a single cycle. With internal loop
counters and loop stacks, the ADMC330 executes looped code
with zero overhead; no explicit jump instructions are required to
maintain the loop.
T wo data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one of
four possible modify registers. A length value may be associated
with each pointer to implement automatic modulo addressing
for circular buffers.
Efficient data transfer is achieved with the use of five internal
buses:
Program Memory Address (PMA) Bus
Program Memory Data (PMD) Bus
Data Memory Address (DMA) Bus
Data Memory Data (DMD) Bus
Result (R) Bus
Program memory can store both instructions and data, permit-
ting the ADMC330 to fetch two operands in a single cycle,
one from program memory and one from data memory. T he
ADMC330 can fetch an operand from on-chip program memory
and the next instruction in the same cycle.
T he ADMC330 can respond to interrupts. T here can be
internal interrupts generated by the T imer, the Serial Ports
(SPORT s), and software or peripheral interrupts generated by
the PIO or PWM. T here is also a master RESET signal.
T he two serial ports provide a complete synchronous serial
interface with optional companding in hardware and a wide
variety of framed or frameless data transmit and receive modes
of operation. Each port can generate an internal programmable
serial clock or accept an external serial clock.
Boot circuitry provides for automatically loading on-chip pro-
gram memory from the data input and output pins on SPORT 1.
SPORT 1 can be alternatively configured as an input flag, output
flag or two additional interrupt sources.
A programmable interval timer generates periodic interrupts. A
16-bit count register (T COUNT ) is decremented every
n
pro-
cessor cycles, where
n-l
is a scaling value stored in an 8-bit regis-
ter (T SCALE). When the value of the count register reaches
zero, an interrupt is generated and the count register is reloaded
from a 16-bit period register (T PERIOD).
T he ADMC330 instruction set provides flexible data moves and
multifunction (one or two data moves with a computation)
instructions. Every instruction can be executed in a single pro-
cessor cycle. T he ADMC330 assembly language uses an alge-
braic syntax for ease of coding and readability. A comprehensive
set of development tools supports program development.
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