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參數(shù)資料
| 型號： | ADMC330BST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Single Chip DSP Motor Controller |
| 中文描述： | 0-BIT, 20 MHz, OTHER DSP, PQFP80 |
| 封裝： | PLASTIC, TQFP-80 |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 163K |
| 代理商： | ADMC330BST |
ADMC330
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REV. 0
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0
PIODIR
PIODATA
(READ/WRITE)
PIOFLAG
(READ-ONLY)
PIOINTEN
(WRITE-ONLY)
0 = INPUT
1 = OUTPUT
1 = HI
0 = LOW
1 = ENABLE INTERRUPT
0 = DISABLE INTERRUPT
1 = INTERRUPT FLAGGED
0 = NO INTERRUPT
PIO0
PIO7
Figure 8. Configuration of PIO Registers
C1
C2
R1
R2
R1 = R2 = 13k
V
C1 = C2 = 10nF
PWMDAC
Figure 7. Auxiliary PWM Output Filter
PROGRAMMABLE DIGIT AL INPUT /OUT PUT
T he ADMC330 has eight programmable digital I/O (PIO) pins:
PIO0–PIO7. Each pin can be individually configurable as either
an input or an output. Input pins can also be used to generate
interrupts.
T he PIO pins are configured as input or output by setting the
appropriate bits in the PIODIR register, as shown in Figure 8.
T he read/write register PIODAT A is used to set the state of an
output pin or read the state of an input pin. Writing to PIODAT A
affects only the pins configured as outputs. T he default state,
after an ADMC330 reset, is that all PIO are configured as inputs.
Any pin can be configured as an independent edge triggered
interrupt source. T he pin must first be configured as an input
and then the appropriate bit must be set in the PIOINT EN
register. A peripheral interrupt is generated when the input level
changes on any PIO pin configured as an interrupt source. A
PIO interrupt sets the appropriate bit in the PIOFLAG register.
T he DSP peripheral interrupt service routine (ISR) must read
the PIOFLAG registers to determine which PIO pin was the
source of the PIO interrupt. Reading the PIOFLAG register will
clear it.
WAT CHDOG T IME R OVE RVIE W
T he watchdog timer can be used to reset the DSP and peripher-
als in the event of a software error hanging the processor. T he
watchdog timer is enabled by writing a value to the watchdog
timer register. In the event of the code “hanging” the counter
will count down from its initial value to zero and the watchdog
timer hardware will force a DSP and peripheral reset. In normal
operation a section of DSP code will write to the timer register
to reset the counter to its initial value preventing it from reach-
ing zero.
DSP CORE ARCHIT E CT URE OVE RVIE W
Figure 9 is a block diagram of the ADMC330 processor core
and system peripherals. T he processor contains three indepen-
dent computational units: T he ALU, the multiplier/accumulator
(MAC) and the shifter. T he computational units process 16-bit
data directly and have provisions to support multiprecision
computations. T he ALU performs a standard set of arithmetic
and logic operations; division primitives are also supported. T he
MAC performs single-cycle multiply, multiply/add and multiply/
subtract operations with 40 bits of accumulation. T he shifter
performs logical and arithmetic shifts, normalization, denormali-
zation and derive exponent operations. T he shifter can be used to
efficiently implement numeric format control including multi-
word and block floating-point representations.
T he internal result (R) bus directly connects the computational
units so that the output of any unit may be the input of any unit
on the next cycle.
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