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ADMC330
–9–
REV. 0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PWMGATE
GATETM
GATE)/(2(GATETM+1))
(f
HCLK
LOW SIDE GATE CHOPPING
HIGH SIDE GATE CHOPPING
1 = ENABLE
0 = DISABLE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
A CHANNEL CROSSOVER
B CHANNEL CROSSOVER
CH OUTPUT DISABLE
CL OUTPUT DISABLE
BH OUTPUT DISABLE
BL OUTPUT DISABLE
AH OUTPUT DISABLE
AL OUTPUT DISABLE
1 = DISABLE
0 = ENABLE
1 = CROSSOVER
0 = NO CROSSOVER
PWMSEG
C CHANNEL CROSSOVER
Figure 4. Configuration of PWMSEG and PWMGATE Registers
T able I. ADC Auxiliary Channel Selection
MODE CT RL (1)
ADCMUX 1
0
0
1
1
MODE CT RL (0)
ADCMUX 0
0
1
0
1
Select
VAUX 0
VAUX 1
VAUX 2
VAUX 3
Analog Block
T he operation of the ADC block may be explained by reference
to Figures 5 and 6. T he reference ramp is tied to one input of
each of the four comparators. T his reference ramp is generated
by charging an external timing capacitor with a constant current
source. T he timing capacitor is connected between pins CAPIN
and SGND. T he capacitor voltage is reset at the start of each
PWM cycle using the PWMSYNC pulse, which is held high for
20 CLK IN cycles (T
CRST
= 2
μ
s for a 10 MHz CLK IN). On the
falling edge of PWMSYNC, the capacitor begins to charge at a
rate determined by the capacitor and the current source values.
An internal current source is made available for connection to
the external timing capacitor on the ICONST pin. An external
current source could also be used, if required. T he four input
comparators of the ADC block continuously compare the values
of the four analog inputs with the capacitor voltage. Each com-
parator output will go high when the capacitor voltage exceeds
the respective analog input voltage.
ADC T imer Block
T he ADC timer block consists of a 12-bit counter clocked at a
constant rate of HCLK , equal to half the DSP clock rate. T his
gives a timer resolution of 100 ns at the maximum CLK IN
frequency of 10 MHz. T he counter is reset on the falling edge of
the PWMSYNC pulse so that the counter commences at the
beginning of the reference voltage ramp. When the output of a
given comparator goes high, the counter value is latched into the
appropriate 12-bit ADC register. T here are four ADC registers
(ADC1, ADC2, ADC3 and ADCAUX ) corresponding to each
of the four comparators. At the end of the reference voltage
ramp, all four registers should have been loaded with new values
so that new conversion data is available to the controller after a
PWMSYNC interrupt.
T he first set of values loaded into the output registers after the
first PWMSYNC interrupt will be invalid since the latched value
is indeterminate. For very low analog inputs, less than the mini-
mum reference value, the comparator output will be perma-
nently high and the output register will contain the code 0x000.
Also, if the input analog voltage exceeds the peak capacitor
ramp voltage, the comparator output will be permanently low
and a 0xFFF code will be produced. T his indicates an input
overvoltage condition.
REFOUT
ICONST
CAPIN
C
SGND
VAUX0
VAUX1
VAUX2
VAUX3
ADC
TIMER
BLOCK
ADC1
ADC2
ADC3
ADCAUX
ADMUX0
ADMUX1
4-1
MUX
V3
V1
V2
PWMSYNC
ADC REGISTERS
HCLK
Figure 5. ADC Overview