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參數(shù)資料
| 型號： | ADMC330 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Single Chip DSP（digital signal processing） Motor Controller(單片的數(shù)字信號處理馬達控制器) |
| 中文描述： | 單芯片DSP（數(shù)字信號處理）電機控制器（單片的數(shù)字信號處理馬達控制器） |
| 文件頁數(shù)： | 17/20頁 |
| 文件大小： | 163K |
| 代理商： | ADMC330 |
ADMC330
–17–
REV. 0
T able VII. Peripheral Register Map
Address
(HE X )
Offset
(Decimal)
Name
Bits Used
Function
0x2000
0x2001
0x2002
0x2003
0x2004
0x2005
0x2006
0x2007
0x2008
0x2009
0x200A
0x200B
0x200C
0x200D
0x200E
0x200F
0x2010
0x2011
0x2012
0x2013
0x2014
0x2015
0x2016
0x2017
0x2018
0x2019..F
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25..31
ADC1
ADC2
ADC3
ADCAUX
PIODIR
PIODAT A
PIOINT EN
PIOFLAG
PWMT M
PWMDT
PWMPD
PWMGAT E
PWMCHA
PWMCHB
PWMCHC
PWMSEG
AUX 0
AUX 1
[4..15]
[4..15]
[4..15]
[4..15]
[0..7]
[0..7]
[0..7]
[0..7]
[0..11]
[0..6]
[0..6]
[0..8]
[0..11]
[0..11]
[0..11]
[0..8]
[0..7]
[0..7]
ADC Results for V1
ADC Results for V2
ADC Results for V3
ADC Results for VAUX
PIO Pins Direction Setting
PIO Pins Input/Output Data
PIO Pins Interrupt Enable
PIO Pins Interrupt Status
PWM Period
PWM Deadtime
PWM Pulse Deletion T ime
PWM Gate Drive Configuration
PWM Channel A Pulsewidth
PWM Channel B Pulsewidth
PWM Channel C Pulsewidth
PWM Segment Select
AUX PWM Output 1
AUX PWM Output 2
Not Used
Not Used
Not Used
System Control Register
System Status
Interrupt Status
Watchdog T imer
Not Used
MODECT RL
SYSST AT
IRQFLAG
WDT IMER
[0..15]
[0..1]
[0..2]
[0..15]
Multiplexer, PWM Interrupts and SPORT 1 Control
T he ADC, the SPORT 1 peripherals and the PWM interrupts
are configured using the MODECT RL register.
1. T wo bits control the ADC aux channel selection:
ADCMUX 0..1.
2. T wo bits can enable/disable the
PWMTRIP
and PWMSYNC
interrupts.
3. T wo bits control the SPORT 1 UART and DR1A/B multiplexer.
T he PWM interrupt enable bits are masking bits rather than
set/reset bits. T herefore, before enabling these interrupts any
pending interrupts can be cleared by reading the IRQFLAG
register.
Setting the UART EN bit connects DR1 to the RFS1 input,
which allows SPORT 1 to be used as a UART port. T he DR1SEL
bit selects either pins DR1A or DR1B. T he reset condition for
all bits in this register is zero.
ADMC330
SPORT1
DR1
TFS1
RFS1
DT1
DR1A
DR1B
TFS1
DT1
SCLCK1
RFS1
SCLCK1
UART
ENABLE
DR1B
SELECT
DEFAULT SWITCH
POSITION SHOWN
Figure 12. Internal Multiplexing of SPORT1 Pins
T he DSP and Peripheral Reset Functions
A full system reset of the ADMC330 is achieved by pulling the
RESET
pin low (for > 5 clock cycles when running, or > 2000
clock cycles on power-up). T his resets the DSP core and all
peripherals including the watchdog timer.
T he SYSST AT register indicates the fault status of the ADMC330
after a
PWMTRIP
interrupt or a watchdog reset:
1. T he status of the
PWMTRIP
pin (active low).
2. T he status of the watchdog flag register (this is not reset on a
DSP
RESET
).
3. T he status of the PWMPOL pin.
When one of the peripherals generates an interrupt, the DSP
IRQ2
line is pulled low and a flag bit is set in the IRQFLAG
register for PWMSYNC and
PWMTRIP
or in the PIOFLAG
register for a PIO interrupt. T he DSP can read these registers to
determine the source of the interrupt. When the IRQFLAG
register is read, the PWMSY NC and
PWMTRIP
bits are
cleared to zero. Reading the PIOFLAG register clears all the bits
in this register to zero. When both registers are cleared, the
IRQ2
line is set high again. T he reset condition for all bits in this regis-
ter is zero.
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相關(guān)代理商/技術(shù)參數(shù) |
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| ADMC330ADVEVALKIT | 制造商:AD 功能描述:330 ANALOG DEVICE S6H1X |
| ADMC330-ADVEVALKIT | 制造商:AD 功能描述:330 ANALOG DEVICE S6H1X |
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| ADMC330KP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AC/DC Motor Controller/Driver |
| ADMC330KP-80 | 制造商:Analog Devices 功能描述: |
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