參數(shù)資料
型號(hào)： ADMC330
廠商： Analog Devices, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： Single Chip DSP（digital signal processing） Motor Controller(單片的數(shù)字信號(hào)處理馬達(dá)控制器)
中文描述： 單芯片DSP（數(shù)字信號(hào)處理）電機(jī)控制器（單片的數(shù)字信號(hào)處理馬達(dá)控制器）
文件頁(yè)數(shù)： 6/20頁(yè)
文件大小： 163K
代理商： ADMC330
ADMC330
–6–
REV. 0
four configuration registers (PWMT M, PWMDT , PWMPD
and PWMGAT E), which define basic waveform parameters
such as the master switching frequency, deadtime, minimum
pulsewidth, and gate drive chopping. T here PWM output sig-
nals on the pins AH through CL are controlled by the input
registers (PWMCHA, PWMCHB, PWMCHC and PWMSEG)
and the control pins
PWMTRIP
and PWMPOL.
PWM Controller Overview
T he PWM controller consists of three units: the center-based
timing unit, output control unit and the gate drive unit as shown
in Figure 1.
T he center-based PWM timing unit is the core of the PWM
controller and produces three pairs of complemented and
deadtime adjusted PWM waveforms as required for ac motor
control.
T he output control unit is a signal switching unit that selects
the appropriate PWM signals to be connected to the output
pins based on the bits set in the segment register (PWMSEG)
as may be required for ECM control or some space vector
modulation schemes.
T he gate drive block sets the logic polarity of the PWM “on”
signal according to the polarity of the PWMPOL pin to match
the gate drive circuit requirement. It can also modulate the
PWM “on” signal with a high frequency carrier (0.08 MHz–
5 MHz) if required for a transformer coupled gate drive circuit.
T he DSP-based control algorithm can be synchronized to the
PWM generator by a hardware interrupt signal that is generated
at the end of every PWM switching cycle. T his same PWMSYNC
signal is internally connected to the internal analog-to-digital
converter and is also available at an output pin. Finally, the
hardware
PWMTRIP
pin can be used to shut down the PWM
controller in the event of a fault.
Center-Based PWM T iming Unit
T he center-based PWM timing unit is a programmable timer
that generates three pairs of fixed frequency PWM waveforms
suitable for controlling a three-phase power inverter. T he unit
contains arithmetic circuits that calculate the PWM signal tim-
ing edges from waveform parameters such as the PWM period,
CENTER-BASED
PWM TIMING
UNIT
PWMTM
PWMCHA
PWMDT
PWMCHB
PWMCHC
CLK
SYNC
RESET
HCLK
PWMSYNC
INTERRUPT
SIGNALS
TIMING CONTROL
REGISTERS
CHANNEL
REGISTERS
OUTPUT
CONTROL
UNIT
SYNC
PWMSEG
OUTPUT CONTROL
REGISTER
PWMGATE
REGISTER
GATE
DRIVE
UNIT
CLK
AH
AL
BH
BL
CH
CL
PWMPOL
PWMTRIP
PWMSYNC
PWMPD
GATE CONTROL
Figure 1. PWM Controller Overview
dead time and the duty cycle for each inverter phase. T here is
no extra DSP software overhead once the duty cycle for each
phase has been calculated and loaded into the PWM channel
registers.
T he PWM T iming Unit produces three pairs of complemented
variable duty cycle waveforms symmetrical about common axes
of the form shown in Figure 2. T hey are complemented wave-
forms, which means that for any pair of PWM waveforms (AH
and AL), they can never both be ON at the same time. T hey are
deadtime adjusted, which means that for any pair of PWM
waveforms, there is a delay between switching from being ON in
one waveform to being ON in the complemented waveform. A
pulse deletion function is implemented, which means that very
narrow PWM pulses will not be generated.
It is important to note that the deadtime compensation does not
take place on the boundary between consecutive PWM cycles.
T hus both the low side and high side devices can switch on
during the transition from a full-ON state to any other state.
T his potentially volatile condition can be avoided by:
Ensuring that the device never enters to the full-ON or full-
OFF states, that is,
PWMCHx
≤
PWMTM
–2
×
(
PWMDT
+ 1),
with PWMPD
= 0
Using an external deadtime compensation circuit.
T here is an active high PWMSYNC pulse produced at the be-
ginning of each PWM cycle to synchronize the operation of
other peripherals with the switching of the power inverter. T his
signal is also internally connected to the ADC block to initiate
conversions, and to the DSP core to generate an interrupt.
Figure 2 shows the center-based PWM operation.
T he master switching frequency can range from 2.5 kHz to
25 kHz and is an integral fraction of HCLK clock frequency. It
is set by the value in the 12-bit PWMT M period register, which
sets the total number of clock cycles in a PWM cycle. T he
required PWM period as a function of the desired master
switching frequency (
f
PWM
) and peripheral system clock fre-
quency (
f
HCLK
) is given by:
PWMTM
=
f
HCLK
f
PWM
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