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參數(shù)資料
| 型號： | ADMC326TN |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 28-Lead ROM-Based DSP Motor Controller |
| 中文描述： | 28 - ROM的鉛基于DSP的電機(jī)控制器 |
| 文件頁數(shù)： | 17/31頁 |
| 文件大?。?/td> | 219K |
| 代理商： | ADMC326TN |
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ADMC326
–17–
REV. A
CHARGING CAPACITOR – nF
0
2
D
50
100
150
200
4
6
8
10
0
Figure 13. PWMSYNCWT Program Value
ADC Resolution
The ADC is intrinsically linked to the PWM block through the
PWMSYNC pulse controlling the ADC conversion process.
Because of this link, the effective resolution of the ADC is a
function of both the PWM switching frequency and the rate at
which the ADC counter timer is clocked. For a CLKOUT period
of t
CK
and a PWM period of T
PWM
, the maximum count of the
ADC is given by:
Max Count
=
min
(4095, (
T
PWM
–
T
CRST
)/2
t
CK
)
for MODECTRL Bit
7 = 0
Max Count
=
min
(4095, (
T
PWM
–
T
CRST
)/
t
CK
)
for MODECTRL Bit
7 = 1
Where
T
PWM
is equal to the PWM period if operating in single
update mode, or it is equal to half that period if operating in
double update mode. For an assumed CLKOUT frequency of
20 MHz and PWMSYNC pulsewidth of 2.0
μ
s, the effective
resolution of the ADC block is tabulated for various PWM
switching frequencies in Table VII.
Table VII. ADC Resolution Examples
PWM
Freq.
(kHz)
MODECTRL[7] = 0
Max
Effective
Count
Resolution
MODECTRL[7] = 1
Max
Effective
Count
Resolution
2.4
4
8
18
25
4095
2480
1230
535
380
12
>11
>10
>9
>8
4095
4095
2460
1070
760
12
12
>11
>10
>9
Charging Capacitor Selection
The charging capacitor value is selected based on the sample
(PWM) frequency desired. A selected capacitor value that is
too small will reduce the available resolution of the ADC by
having the ramp voltage rise rapidly and convert too quickly,
not utilizing all possible counts available in the PWM cycle. Too
large a capacitor may not convert in the available PWM cycle,
returning 0xFFF. To select a charging capacitor use Figure 14,
select the sampling frequency desired, then determine if the cur-
rent source is to be tuned to a nominal 100
μ
A or left in the
default (0x0 code) trim state, then determine the proper charge
capacitor from the appropriate curve.
PWM FREQUENCY – kHz
100
11
100
10
C
N
10
DEFAULT ICONST
TUNED ICONST
Figure 14. Timing Capacitor Selection
Programmable Current Source
The ADMC326 has an internal current source that is used to
charge an external capacitor, generating the voltage ramp used
for conversion. The magnitude of the output of the current source
circuit is subject to manufacturing variations and can vary from
one device to the next. Therefore, the ADMC326 incudes a pro-
grammable current source whose output can always be tuned to
within 5% of the target 100
μ
A. A 3-bit register, ICONST_TRIM,
allows the user to make this adjustment. The output current is
proportional to the value written to the register: 0x0 produces
the minimum output, and 0x7 produces the maximum output.
The default value of ICONST_TRIM after reset is 0x0.
ADC Reference Ramp Calibration
The peak of the ADC ramp voltage should be as close as pos-
sible to 3.5 V to achieve the optimum ADC resolution and
signal range. When the current source is in the Default State,
the peak of the ADC ramp slope will be lower than this “3.5 V”
target ramp. When the current source value is increased, the
ADC ramp slope will become closer to the target value. The
“tuned” ramp slope is the one closest to the target ramp.
A simple calibration procedure using the internal 2.5 V reference
voltage allows the selection of the ICONST_TRIM register
value to reach this “tuned” ramp slope:
1. A high quality linear ADC capacitor is selected using Figure
14 for a tuned ICONST.
2. Program PWMSYNCWT to proper count as in Figure 13.
3. The ADC Max Count is calculated, as described in the ADC
Resolution section.
4. The target reference conversion count is calculated as TAR-
GET = (Max Count)
×
(2.5 V/3.5 V).
5. Reset or software sets the ICONST_TRIM register to zero.
6. Select the calibration V
REF
in software on ADC multiplexer
and wait one PWM cycle for updated ADC value.
7. The calibration channel value is compared with the target
reference conversion.
8. If this value is greater than the TARGET, the ICONST_TRIM
value is incremented by one, and Step 7 is repeated.
9. If the calibration channel value is less than the TARGET, the
calibration is completed.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADMC326TR | 28-Lead ROM-Based DSP Motor Controller |
| ADMC326YN | 28-Lead ROM-Based DSP Motor Controller |
| ADMC326YR | 28-Lead ROM-Based DSP Motor Controller |
| ADMC326 | 28-Lead ROM-Based DSP Motor Controller |
| ADMC328 | 28-Lead ROM-Based DSP Motor Controller(28腳含ROM、數(shù)字信號處理的的馬達(dá)控制器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADMC326TN-XXX-YY | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MOTOR CONTROLLER |
| ADMC326TR | 制造商:AD 制造商全稱:Analog Devices 功能描述:28-Lead ROM-Based DSP Motor Controller |
| ADMC326TR-XXX-YY | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MOTOR CONTROLLER |
| ADMC326YN | 制造商:AD 制造商全稱:Analog Devices 功能描述:28-Lead ROM-Based DSP Motor Controller |
| ADMC326YN-XXX-YY | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MOTOR CONTROLLER |
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