參數(shù)資料
型號: ADMC326TN
廠商: Analog Devices, Inc.
英文描述: 28-Lead ROM-Based DSP Motor Controller
中文描述: 28 - ROM的鉛基于DSP的電機控制器
文件頁數(shù): 11/31頁
文件大?。?/td> 219K
代理商: ADMC326TN
ADMC326
–11–
REV. A
state. Because this hardware shutdown mechanism is asynchro-
nous, and the associated PWM disable circuitry does not use
clocked logic, the PWM will shut down even if the DSP clock is
not running. The PWM system may also be shut down from
software by writing to the PWMSWT register.
Status information about the PWM system of the ADMC326 is
available to the user in the SYSSTAT register. In particular, the
state of
PWMTRIP
is available, as well as a status bit that indi-
cates whether operation is in the first half or the second half of
the PWM period.
A functional block diagram of the PWM controller is shown in
Figure 6. The generation of the six output PWM signals on pins
AH to CL is controlled by four important blocks:
The three-phase PWM timing unit, which is the core of the
PWM controller, generates three pairs of complemented and
dead-time-adjusted center-based PWM signals.
The output control unit allows the redirection of the outputs
of the three-phase timing unit for each channel to either the
high side or the low side output. In addition, the output con-
trol unit allows individual enabling/disabling of each of the six
PWM output signals.
The GATE drive unit provides the high chopping frequency
and its subsequent mixing with the PWM signals.
The PWM shutdown controller manages the three PWM
shutdown modes (via the
PWMTRIP
pin, the analog block or
the PWMSWT register) and generates the correct
RESET
signal
for the Timing Unit.
The PWM controller is driven by a clock at the same frequency
as the DSP instruction rate, CLKOUT, and is capable of
generating two interrupts to the DSP core. One interrupt is
generated on the occurrence of a PWMSYNC pulse, and the
other is generated on the occurrence of any PWM shutdown
action.
PWMTRIP
OR
PWMSWT (0)
PWM SHUTDOWN CONTROLLER
PWMTRIP
PWMSEG (8...0)
OUTPUT
CONTROL
UNIT
GATE
DRIVE
UNIT
CLK
PWM DUTY CYCLE
REGISTERS
PWM CONFIGURATION
REGISTERS
TO INTERRUPT
CONTROLLER
THREE-PHASE
PWM TIMING
UNIT
CLK
RESET
SYNC
SYNC
PWMSYNC
CLKOUT
AH
AL
BH
BL
CH
CL
PWMGATE (9...0)
PWMTM (15...0)
PWMDT (9...0)
PWMPD (15...0)
PWMSYNCWT (7...0)
MODECTRL (6)
PWMCHA (15...0)
PWMCHB (15...0)
PWMCHC (15...0)
Figure 6. Overview of the PWM Controller of the ADMC326
Three-Phase Timing Unit
The 16-bit three-phase timing unit is the core of the PWM con-
troller and produces three pairs of pulsewidth modulated signals
with high resolution and minimal processor overhead. There are
four main configuration registers (PWMTM, PWMDT, PWMPD
and PWMSYNCWT) that determine the fundamental charac-
teristics of the PWM outputs. In addition, the operating mode
of the PWM (single or double update mode) is selected by Bit 6
of the MODECTRL register. These registers, in conjunction with
the three 16-bit duty cycle registers (PWMCHA, PWMCHB and
PWMCHC), control the output of the three-phase timing unit.
PWM Switching Frequency: PWMTM Register
The PWM switching frequency is controlled by the PWM
period register, PWMTM. The fundamental timing unit of
the PWM controller is t
CK
= 1/f
CLKOUT
where f
CLKOUT
is the
CLKOUT frequency (DSP instruction rate). Therefore, for a
20 MHz CLKOUT, the fundamental time increment is 50 ns.
The value written to the PWMTM register is effectively the
number of t
CK
clock increments in half a PWM period. The
required PWMTM value is a function of the desired PWM
switching frequency (f
PWM
) and is given by:
f
CLKOUT
=
×
2
PWMTM
f
f
f
PWM
CLKIN
PWM
=
Therefore, the PWM switching period, T
S
, can be written as:
T
PWMTM
S
2
For example, for a 20 MHz CLKOUT and a desired PWM
switching frequency of 10 kHz (T
S
= 100
μ
s), the correct value
to load into the PWMTM register is:
t
CK
=
×
×
PWMTM
x E
0 3 8
=
×
×
×
=
20
10
2
10
10
1000
6
3
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