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參數(shù)資料
| 型號(hào)： | ADM1028ARQZ-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO16 |
| 封裝： | MO-137AB, QSOP-16 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大小： | 379K |
| 代理商： | ADM1028ARQZ-REEL7 |
REV. B
ADM1028
–7–
condition. In READ mode, the master device will override
the acknowledge bit by pulling the data line high during the
low period before the ninth clock pulse. This is known as
No Acknowledge. The master will then take the data line low
during the low period before the tenth clock pulse, then high
during the tenth clock pulse to assert a STOP condition.
Any number of bytes of data may be transferred over the serial
bus in one operation, but it is not possible to mix read and write
in one operation, because the type of operation is determined at
the beginning and cannot subsequently be changed without
starting a new operation.
In the case of the ADM1028, write operations contain either one
or two bytes, and read operations contain one byte, and perform
the following functions:
To write data to one of the device data registers or read data
from it, the Address Pointer Register must be set so that the correct
data register is addressed, then data can be written into that
register or read from it. The first byte of a write operation always
contains an address that is stored in the Address Pointer Register.
If data is to be written to the device, the write operation contains
a second data byte that is written to the register selected by the
address pointer register.
This is illustrated in Figure 2a. The device address is sent over
the bus followed by R/
W set to 0. This is followed by two data
bytes. The first data byte is the address of the internal data
register to be written to, which is stored in the Address Pointer
Register. The second data byte is the data to be written to the
internal data register.
When reading data from a register there is only one possibility:
1. The serial bus address is written to the device along with the
address pointer register value. The ADM1028 should then
acknowledge the write by pulling SDA low during the ninth
clock pulse. The master does not generate a STOP condition
but issues a new START condition. The serial bus address
is again sent but with the R/
W bit high, indicating a READ
operation. The ADM1028 will then return the data from the
selected register, and a No Acknowledge is generated to signify
the end of the read operation. The master will then initiate a
STOP condition to end the transaction and release the SMBus.
In Figures 2a and 2b, the serial bus address is shown as the
default value 0101110.
R/
W
0
SCL
SDA
10
1
10
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
ADM1028
START BY
MASTER
19
1
ACK. BY
ADM1028
9
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
ADM1028
1
9
SCL (CONTINUED)
SDA (CONTINUED)
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
FRAME 3
DATA BYTE
1
STOP BY
MASTER
Figure 2a. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register
R/
W
0
SCL
SDA
10
1
0
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
ADM1028
START BY
MASTER
19
1
ACK. BY
ADM1028
9
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
R/
W
0
SCL
SDA
10
1
0
D7
D6
D5
D4
D3
D2
D1
D0
NO ACK.
BY MASTER
START BY
MASTER
19
1
ACK. BY
ADM1028
9
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
DATA BYTE FROM ADM1028
STOP BY
MASTER
Figure 2b. Reading Data from the ADM1028
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