參數(shù)資料
型號： ADM1027ARQZ-RL7
廠商： ON Semiconductor
文件頁數(shù)： 48/56頁
文件大?。?/td> 1822K
描述： IC REMOTE THERMAL CTLR 24QSOP
產(chǎn)品變化通告： MFG CHG Notification ADI to ON Semi
Product Discontinuation Notice 25/Aug/2008
Product Obsolescence 30/Sept/2009
標準包裝： 1,000
系列： dBCool®
功能： 風扇控制，溫度監(jiān)控器
傳感器類型： 內(nèi)部和外部
感應(yīng)溫度： 0°C ~ 105°C，外部傳感器
精確度： ±1°C
拓撲： ADC，比較器，風扇速度計數(shù)器，多路復(fù)用器，寄存器庫
輸出類型： SMBus?
輸出警報： 無
輸出風扇： 是
電源電壓： 3 V ~ 5.5 V
工作溫度： 0°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 24-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 24-QSOP
包裝： 帶卷 (TR)
REV. A
48
ADM1027
Table XVIII. Register 0x62  Enhance Acoustics Register 1 (Power-On Default = 0x00)
Bit
Name
R/W
Description
<2:0>
ACOU
Read-Only
These bits select the ramp rate applied to the PWM1 output. Instead of PWM1 jump-
ing instantaneously to its newly calculated speed, PWM1 will ramp gracefully at the rate
determined by these bits. This feature enhances the acoustics of the fan being driven by
the PWM1 output.
Time slot increase
Time for 33% to 100%
000 = 1
35 sec
001 = 2
17.6 sec
010 = 3
1.8 sec
011 = 5
7 sec
100 = 8
4.4 sec
101 = 12
3 sec
110 = 24
1.6 sec
111 = 48
0.8 sec
<3>
EN1
Read/Write
When this bit is 1, acoustic enhancement is enabled on PWM1 output. When
acoustic enhancement is enabled, fan spin-up time should be disabled.
<4>
Reserved
Read-Only
Reserved for future use.
<5>
MIN1
Read/Write
When the ADM1027 is in automatic fan control mode, this bit defines whether PWM 1
is off (0% duty cycle) or at PWM 1 minimum duty cycle when the controlling temperature
is below its T
MIN
  hysteresis value.
0 = 0% duty cycle below T
MIN
 hysteresis
1 = PWM 1 minimum duty cycle below T
MIN
 hysteresis
<6>
MIN2
Read/Write
When the ADM1027 is in automatic fan speed control mode, this bit defines whether
PWM 2 is off (0% duty cycle) or at PWM 2 minimum duty cycle when the controlling
temperature is below its T
MIN
  hysteresis value.
0 = 0% duty cycle below T
MIN
 hysteresis
1 = PWM 2 minimum duty cycle below T
MIN
 hysteresis
<7>
MIN3
Read/Write
When the ADM1027 is in automatic fan speed control mode, this bit defines whether
PWM 3 is off (0% duty cycle) or at PWM 3 minimum duty cycle when the controlling
temperature is below its T
MIN
  hysteresis value.
0 = 0% duty cycle below T
MIN
  hysteresis
1 = PWM 3 minimum duty cycle below T
MIN
 hysteresis
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register
will have no effect.
Rev. 3 | Page 48 of 56 | www.onsemi.com
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