參數(shù)資料
型號(hào): ADM1027ARQZ-RL7
廠商: ON Semiconductor
文件頁(yè)數(shù): 26/56頁(yè)
文件大?。?/td> 1822K
描述: IC REMOTE THERMAL CTLR 24QSOP
產(chǎn)品變化通告: MFG CHG Notification ADI to ON Semi
Product Discontinuation Notice 25/Aug/2008
Product Obsolescence 30/Sept/2009
標(biāo)準(zhǔn)包裝: 1,000
系列: dBCool®
功能: 風(fēng)扇控制,溫度監(jiān)控器
傳感器類(lèi)型: 內(nèi)部和外部
感應(yīng)溫度: 0°C ~ 105°C,外部傳感器
精確度: ±1°C
拓?fù)洌?/td> ADC,比較器,風(fēng)扇速度計(jì)數(shù)器,多路復(fù)用器,寄存器庫(kù)
輸出類(lèi)型: SMBus?
輸出警報(bào): 無(wú)
輸出風(fēng)扇:
電源電壓: 3 V ~ 5.5 V
工作溫度: 0°C ~ 105°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 24-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 24-QSOP
包裝: 帶卷 (TR)
REV. A
26
ADM1027
MANUAL FAN SPEED CONTROL MODE
PWM Logic State
The PWM outputs can be programmed to be high for 100%
duty cycle (noninverted) or low for 100% duty cycle (inverted).
PWM1 Configuration (Reg. 0x5C)
<4> INV
0 = logic high for 100% PWM duty cycle
1 = logic low for 100% PWM duty cycle
PWM2 Configuration (Reg. 0x5D)
<4> INV
0 = logic high for 100% PWM duty cycle
1 = logic low for 100% PWM duty cycle
PWM3 Configuration (Reg. 0x5E)
<4> INV
0 = logic high for 100% PWM duty cycle
1 = logic low for 100% PWM duty cycle
PWM Drive Frequency
The PWM drive frequency can be adjusted for the application.
Registers 0x5F to 0x61 configure the PWM frequency for
PWM1 to PWM3, respectively.
PWM1 FREQUENCY REGISTERS (REG. 0x5F to 0x61)
<2:0> FREQ
000 = 11.0 Hz
001 = 14.7 Hz
010 = 22.1 Hz
011 = 29.4 Hz
100 = 35.3 Hz (default)
101 = 44.1 Hz
110 = 58.8 Hz
111 = 88.2 Hz
Manual Fan Speed Control
The ADM1027 allows the duty cycle of any PWM output to be
manually adjusted. This can be useful if you want to change fan
speed in software or want to adjust PWM duty cycle output for
test purposes. Bits <7:5> of Registers 0x5C to 0x5E (PWM
configuration) control the behavior of each PWM output.
PWM CONFIGURATION (REG. 0x5C to 0x5E)
<7:5> BHVR 111 = Manual Mode
Once under manual control, each PWM output may be manually
updated by writing to Registers 0x30 to 0x32 (PWMx current
duty cycle registers).
Programming the PWM
 
Current Duty Cycle Registers
The PWM
 
current duty cycle registers are 8-bit registers that
allow the PWM duty cycle for each output to be set anywhere
from 0% to 100%. This allows the PWM duty cycle to be set in
steps of 0.39%.
The value to be programmed into the PWM
MIN
 register is
given by
 
 
Value  decimal
PWM
MIN
(
)
=
0 39
.
Example 1: for a PWM duty cycle of 50%,
Value (decimal) = 50/0.39 = 128 decimal
Value = 128 decimal or 80 hex.
Example 2: for a PWM duty cycle of 33%,
Value (decimal) = 33/0.39 = 85 decimal
Value = 85 decimal or 54 hex.
PWM Duty Cycle Registers
Reg. 0x30 PWM1 Duty Cycle = 0xFF (100% default)
Reg. 0x31 PWM2 Duty Cycle = 0xFF (100% default)
Reg. 0x32 PWM3 Duty Cycle = 0xFF (100% default)
By reading the PWMx current duty cycle registers, you can keep
track of the current duty cycle on each PWM output, even when
the fans are running in automatic fan speed control mode or
acoustic enhancement mode.
Rev. 3 | Page 26 of 56 | www.onsemi.com
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