參數(shù)資料
型號: ADF7020BCP
廠商: ANALOG DEVICES INC
元件分類: 無繩電話/電話
英文描述: High Performance ISM Band FSK/ASK Transceiver IC
中文描述: TELECOM, CELLULAR, RF AND BASEBAND CIRCUIT, QCC48
封裝: 7 X 7 MM, LFCSP-48
文件頁數(shù): 9/40頁
文件大?。?/td> 797K
代理商: ADF7020BCP
Preliminary Technical Data
ADF7020
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. PrH | Page 9 of 40
36
35
34
33
32
31
30
29
28
27
26
25
4
4
4
4
4
4
4
4
4
3
3
3
1
1
1
1
1
1
1
2
2
2
2
2
ADF7020
TOP VIEW
(Not to Scale)
VCOIN
VREG1
VDD1
RFOUT
RFGND
RFIN
RFINB
R
LNA
VDD4
RSET
VREG4
GND4
M
M
M
M
F
F
G
F
F
G
T
C
CLKOUT
DATA CLK
DATA I/O
INT/LOCK
VDD2
VREG2
ADCIN
GND2
SCLK
SREAD
SDATA
SLE
C
G
G
V
G
V
C
V
V
O
O
M
1
2
3
4
5
6
7
8
9
10
11
12
PIN 1
0
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
1
VCOIN
Function
The tuning voltage on this pin determines the output frequency of the voltage controlled oscillator (VCO).
The higher the tuning voltage, the higher the output frequency.
Regulator Voltage for PA Block. A 100 nF capacitor should be placed between this pin and ground for
regulator stability and noise rejection.
Voltage Supply for PA Block. Decoupling capacitors (X7R or Tantalum) of 0.1 μF and 0.01 μF should be placed
as close as possible to this pin.
The modulated signal is available at this pin. Output power levels are from 20 dBm to +13 dBm. The output
should be impedance matched to the desired load using suitable components. See the Transmitter section.
Ground for Output Stage of Transmitter.
LNA Input for Receiver Section. Input matching is required between the antenna and the differential LNA
input to ensure maximum power transfer. See the LNA/PA Matching section.
Complementary LNA Input. See the LNA/PA Matching section.
External bias resistor for LNA. Optimum resistor is 1.1 k with 5% tolerance.
Voltage supply for LNA/MIXER block. This pin should be decoupled to ground with a 0.01 μF capacitor.
External Resistor to Set Charge Pump Current and Some Internal Bias Currents. Use 3.6 k with 5% tolerance.
Regulator Voltage for LNA/MIXER block. A 100 nF capacitor should be placed between this pin and GND for
regulator stability and noise rejection.
Ground for LNA/MIXER block.
Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left
unconnected.
Ground for LNA/MIXER block.
Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left
unconnected.
Chip Enable. Bringing CE low puts the ADF7020 into complete power-down. Register values are lost when CE
is low, and the part must be reprogrammed once CE is brought high.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the
four latches. A latch is selected using the control bits.
Serial Data Input. The serial data is loaded MSB first with the two LSBs as the control bits. This pin is a high
impedance CMOS input.
Serial Data Output. This pin is used to feed readback data from the ADF7020 to the microcontroller. The SCLK
input is used to clock each readback bit (AFC, ADC readback) from the SREAD pin.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into
the 24-bit shift register on the CLK rising edge. This pin is a digital CMOS input.
2
VREG1
3
VDD1
4
RFOUT
5
6
RFGND
RFIN
7
8
9
10
11
RFINB
R
LNA
VDD4
RSET
VREG4
12
13–18
GND4
MIX/FILT
19, 22
20, 21, 23
GND4
FILT/TEST_A
24
CE
25
SLE
26
SDATA
27
SREAD
28
SCLK
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