參數(shù)資料
型號(hào)： ADF7020BCP
廠商： ANALOG DEVICES INC
元件分類： 無(wú)繩電話/電話
英文描述： High Performance ISM Band FSK/ASK Transceiver IC
中文描述： TELECOM, CELLULAR, RF AND BASEBAND CIRCUIT, QCC48
封裝： 7 X 7 MM, LFCSP-48
文件頁(yè)數(shù)： 11/40頁(yè)
文件大?。?/td> 797K
代理商： ADF7020BCP
Preliminary Technical Data
ADF7020
FREQUENCY SYNTHESIZER
REFERENCE INPUT SECTION
The on-board crystal oscillator circuitry (Figure 5) can use an
inexpensive quartz crystal as the PLL reference. The oscillator
circuit is enabled by setting R1_DB12 high. It is enabled by
default on power-up and is disabled by bringing CE low. Errors
in the crystal can be corrected using the automatic frequency
control (see the AFC Section) feature or by adjusting the
fractional-N value (see the N Counter section). A single-ended
reference (TCXO, CXO) can also be used. The CMOS levels
should be applied to OSC2 with R1_DB12 set low.
Rev. PrH | Page 11 of 40
OSC1
CP1
CP2
OSC2
0
Figure 5. Oscillator Circuit on the ADF7020
Two parallel resonant capacitors are required for oscillation at
the correct frequency; their values are dependent on the crystal
specification. They should be chosen so that the series value of
capacitance added to the PCB track capacitance adds up to the
load capacitance of the crystal, usually 20 pF. Track capacitance
values vary from 2 pF to 5 pF, depending on board layout.
Where possible, choose capacitors that have a very low
temperature coefficient to ensure stable frequency operation
over all conditions.
CLKOUT Divider and Buffer
The CLKOUT circuit takes the reference clock signal from the
oscillator section, shown in Figure 5, and supplies a divided-
down 50:50 mark-space signal to the CLKOUT pin. An even
divide from 2 to 30 is available. This divide number is set in
R1_DB(8:11). On power-up, the CLKOUT defaults to
divide-by-8.
DV
DD
CLK
ENABLE BIT
CLK
OUT
OSC1
DIVIDER
1 TO 15
0
÷
2
Figure 6. CLK
OUT
Stage
To disable CLKOUT, set the divide number to 0. The output
buffer can drive up to a 20 pF load with a 10% rise time at
4.8 MHz. Faster edges can result in some spurious feedthrough
to the output. A small series resistor (50 ) can be used to slow
the clock edges to reduce these spurs at F
CLK
.
R Counter
The 3-bit R counter divides the reference input frequency by an
integer from 1 to 7. The divided-down signal is presented as the
reference clock to the phase frequency detector (PFD). The
divide ratio is set in Register 1. Maximizing the PFD frequency
reduces the N value. This reduces the noise multiplied at a rate
of 20 log(N) to the output, as well as reducing occurrences of
spurious components. The R Register defaults to R = 1 on
power-up:
PFD
[Hz] =
XTAL/R
MUXOUT and Lock Detect
The MUXOUT pin allows the user to access various digital
points in the ADF7020. The state of MUXOUT is controlled by
Bits R0_DB(29:31).
Regulator Ready
REGULATOR READY is the default setting on MUXOUT after
the transceiver has been powered up. The power-up time of the
regulator is typically 50 μs. Because the serial interface is
powered from the regulator, the regulator must be at its nominal
voltage before the ADF7020 can be programmed. The status of
the regulator can be monitored at MUXOUT. When the
REGULATOR READY signal on MUXOUT is high,
programming of the ADF7020 can begin.
REGULATOR READY
DIGITAL LOCK DETECT
ANALOG LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
PLL TEST MODES
Σ
-
TEST MODES
MUX
CONTROL
DGND
DV
DD
MUXOUT
0
Figure 7. MUXOUT Circuit
Digital Lock Detect
Digital lock detect is active high. The lock detect circuit is
located at the PFD. When the phase error on five consecutive
cycles is less than 15 ns, lock detect is set high. Lock detect
remains high until 25 ns phase error is detected at the PFD.
Because no external components are needed for digital lock
detect, it is more widely used than analog lock detect.
相關(guān)PDF資料
PDF描述
ADG1204 2 pF Off Capacitance, 1 pC Charge Injection, +-15 V/12 V 4:1 iCMOS Multiplexer
ADG1204YCP 2 pF Off Capacitance, 1 pC Charge Injection, +-15 V/12 V 4:1 iCMOS Multiplexer
ADG1204YRU 2 pF Off Capacitance, 1 pC Charge Injection, +-15 V/12 V 4:1 iCMOS Multiplexer
ADG202A Quad SPST Switches(LC2MOS四單刀單擲開(kāi)關(guān))
ADG201A Quad SPST Switches(LC2MOS四單刀單擲開(kāi)關(guān))
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADF7020BCP-REEL 制造商:Analog Devices 功能描述:RF TRNSCVR ASK/FSK 2.5V/3.3V 48LFCSP EP - Tape and Reel
ADF7020BCP-REEL7 制造商:Analog Devices 功能描述:RF TRNSCVR ASK/FSK 2.5V/3.3V 48LFCSP EP - Tape and Reel
ADF7020BCP-U1 制造商:Analog Devices 功能描述:HIGH PERFORMANCE ISM BAND FSK/ASK TRANSCEIVER IC - Trays
ADF7020BCPZ 功能描述:IC TX FSK/ASK ISM BAND 48LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 收發(fā)器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:30 系列:- 頻率:4.9GHz ~ 5.9GHz 數(shù)據(jù)傳輸率 - 最大:54Mbps 調(diào)制或協(xié)議:* 應(yīng)用:* 功率 - 輸出:-3dBm 靈敏度:- 電源電壓:2.7 V ~ 3.6 V 電流 - 接收:* 電流 - 傳輸:* 數(shù)據(jù)接口:PCB，表面貼裝 存儲(chǔ)容量:- 天線連接器:PCB，表面貼裝 工作溫度:-25°C ~ 85°C 封裝/外殼:68-TQFN 裸露焊盤(pán) 包裝:管件
ADF7020BCPZ-RL 功能描述:IC TX FSK/ASK ISM BAND 48LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 收發(fā)器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:30 系列:- 頻率:4.9GHz ~ 5.9GHz 數(shù)據(jù)傳輸率 - 最大:54Mbps 調(diào)制或協(xié)議:* 應(yīng)用:* 功率 - 輸出:-3dBm 靈敏度:- 電源電壓:2.7 V ~ 3.6 V 電流 - 接收:* 電流 - 傳輸:* 數(shù)據(jù)接口:PCB，表面貼裝 存儲(chǔ)容量:- 天線連接器:PCB，表面貼裝 工作溫度:-25°C ~ 85°C 封裝/外殼:68-TQFN 裸露焊盤(pán) 包裝:管件
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*