參數(shù)資料
型號(hào): ADF7020BCP
廠商: ANALOG DEVICES INC
元件分類: 無繩電話/電話
英文描述: High Performance ISM Band FSK/ASK Transceiver IC
中文描述: TELECOM, CELLULAR, RF AND BASEBAND CIRCUIT, QCC48
封裝: 7 X 7 MM, LFCSP-48
文件頁數(shù): 30/40頁
文件大小: 797K
代理商: ADF7020BCP
ADF7020
Preliminary Technical Data
REGISTER 3—RECEIVER CLOCK REGISTER
Rev. PrH | Page 30 of 40
FS8
0
0
.
1
1
FS7
0
0
.
1
1
FS3
0
0
.
1
1
...
...
...
...
...
...
FS2
0
1
.
1
1
FS1
1
0
.
0
1
CDR_CLK_DIVIDE
1
2
.
254
255
BK2
0
0
1
BK1
0
1
x
BBOS_CLK_DIVIDE
4
8
16
SK8
0
0
.
1
1
SK7
0
0
.
1
1
SK3
0
0
.
1
1
...
...
...
...
...
...
SK2
0
1
.
1
1
SK1
1
0
.
0
1
SEQ_CLK_DIVIDE
1
2
.
254
255
OK2
0
0
1
1
OK1
0
1
0
1
DEMOD_CLK_DIVIDE
4
1
2
3
SEQUENCER CLOCK DIVIDE
CDR CLOCK DIVIDE
B
C
D
C
ADDRESS
BITS
S
S
F
F
F
F
F
S
S
S
S
S
F
F
F
O
O
C
C
C
C
B
B
I
I
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
0
Figure 31.
Notes:
1.
Baseband offset clock frequency (BBOS_CLK) must be greater than 1 MHz and less than 2 MHz, where:
DIVIDE
CLK
BBOS
XTAL
CLK
BBOS
_
_
_
=
2.
The demodulator clock (DEMOD_CLK) must be < 12 MHz for FSK and < 6 MHz for ASK, where:
DIVIDE
CLK
DEMOD
XTAL
_
CLK
DEMOD
_
_
=
3.
Data/clock recovery frequency (CDR_CLK) should be within 2% of (32 × data rate), where:
CLK
DEMOD
CLK
CDR
_
_
DIVIDE
CLK
CDR
_
_
=
Note that this might affect your choice of XTAL, depending on the desired data rate.
4.
The sequencer clock (SEQ_CLK) supplies the clock to the digital receive block. It should be close to 100 kHz for FSK and close to 40 kHz for ASK:
XTAL
CLK
SEQ
_
_
DIVIDE
CLK
SEQ
_
=
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