參數(shù)資料
| 型號： | ADF4351BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 19/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTH PLL VCO 32LFCSP |
| 標準包裝： | 1 |
| 類型： | 扇出配送，分數(shù)-N，整數(shù)-N，時鐘/頻率合成器（RF） |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:3 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 4.4GHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 32-LFCSP（5x5） |
| 包裝： | 托盤 |
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ADF4351
Data Sheet
Rev. 0 | Page 26 of 28
INTERFACING TO THE ADuC70xx AND
The ADF4351 has a simple SPI-compatible serial interface for
writing to the device. The CLK, DATA, and LE pins control the
data transfer. When LE goes high, the 32 bits that were clocked
into the appropriate register on each rising edge of CLK are
transferred to the appropriate latch. See Figure 2 for the timing
diagram and Table 6 for the register address table.
ADuC70xx Interface
Figure 35 shows the interface between the ADF4351 and the
ADuC70xx family of analog microcontrollers. The ADuC70xx
family is based on an AMR7 core, but the same interface can be
used with any 8051-based microcontroller.
ADuC70xx
ADF4351
CLK
DATA
LE
CE
MUXOUT
(LOCK DETECT)
SCLOCK
MOSI
I/O PORTS
09800-
035
Figure 35. ADuC70xx to ADF4351 Interface
The microcontroller is set up for SPI master mode with CPHA =
0. To initiate the operation, the I/O port driving LE is brought
low. Each latch of the ADF4351 needs a 32-bit word, which is
accomplished by writing four 8-bit bytes from the micro-
controller to the device. After the fourth byte is written, the
LE input should be brought high to complete the transfer.
When power is first applied to the ADF4351, the part requires
six writes (one each to R5, R4, R3, R2, R1, and R0) for the output
to become active.
I/O port lines on the microcontroller are also used to control
the power-down input (CE) and to detect lock (MUXOUT
configured as lock detect and polled by the port input).
When operating in the mode described, the maximum SPI
transfer rate of the ADuC70xx is 20 Mbps. This means that
the maximum rate at which the output frequency can be
changed is 833 kHz. If using a faster SPI clock, make sure that
the SPI timing requirements listed in Table 2 are adhered to.
ADSP-BF527 Interface
Figure 36 shows the interface between the ADF4351 and the
Blackfin ADSP-BF527 digital signal processor (DSP). The
ADF4351 needs a 32-bit serial word for each latch write. The
easiest way to accomplish this using the Blackfin family is to
use the autobuffered transmit mode of operation with alternate
framing. This mode provides a means for transmitting an entire
block of serial data before an interrupt is generated.
ADSP-BF527
ADF4351
CE
MUXOUT
(LOCK DETECT)
I/O PORTS
CLK
SCK
DATA
MOSI
LE
GPIO
09800-
036
Figure 36. ADSP-BF527 to ADF4351 Interface
Set up the word length for eight bits and use four memory
locations for each 32-bit word. To program each 32-bit latch,
store the four 8-bit bytes, enable the autobuffered mode, and
write to the transmit register of the DSP. This last operation
initiates the autobuffer transfer. Make sure that the SPI timing
requirements listed in Table 2 are adhered to.
PCB DESIGN GUIDELINES FOR A CHIP SCALE
PACKAGE
The lands on the chip scale package (CP-32-2) are rectangular.
The PCB pad for these lands must be 0.1 mm longer than the
package land length and 0.05 mm wider than the package land
width. Each land must be centered on the pad to ensure that the
solder joint size is maximized.
The bottom of the chip scale package has a central exposed thermal
pad. The thermal pad on the PCB must be at least as large as the
exposed pad. On the PCB, there must be a minimum clearance
of 0.25 mm between the thermal pad and the inner edges of the
pad pattern to ensure that shorting is avoided.
Thermal vias can be used on the PCB thermal pad to improve
the thermal performance of the package. If vias are used, they
must be incorporated into the thermal pad at 1.2 mm pitch grid.
The via diameter must be between 0.3 mm and 0.33 mm, and
the via barrel must be plated with 1 oz. of copper to plug the via.
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| ADF4351BCPZ-RL7 | 功能描述:IC SYNTH PLL VCO 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
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