參數(shù)資料
| 型號： | ADF4351BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/28頁 |
| 文件大小： | 0K |
| 描述： | IC SYNTH PLL VCO 32LFCSP |
| 標準包裝： | 1 |
| 類型： | 扇出配送，分數(shù)-N，整數(shù)-N，時鐘/頻率合成器（RF） |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:3 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 4.4GHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 32-LFCSP（5x5） |
| 包裝： | 托盤 |
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Data Sheet
ADF4351
Rev. 0 | Page 23 of 28
FAST LOCK LOOP FILTER TOPOLOGY
To use fast lock mode, the damping resistor in the loop filter is
reduced to one-fourth its value while in wide bandwidth mode.
To achieve the wider loop filter bandwidth, the charge pump
current increases by a factor of 16; to maintain loop stability,
the damping resistor must be reduced by a factor of one-fourth.
To enable fast lock, the SW pin is shorted to the AGND pin by
setting Bits[DB16:DB15] in Register 3 to 01. The following two
topologies are available:
The damping resistor (R1) is divided into two values
(R1 and R1A) that have a ratio of 1:3 (see Figure 31).
An extra resistor (R1A) is connected directly from SW, as
shown in Figure 32. The extra resistor is calculated such
that the parallel combination of the extra resistor and the
damping resistor (R1) is reduced to one-fourth the original
value of R1 (see Figure 32).
ADF4351
CPOUT
SW
C1
C2
R2
R1
R1A
C3
VCO
098
00-
0
18
Figure 31. Fast Lock Loop Filter Topology 1
ADF4351
CPOUT
SW
C1
C2
R2
R1
R1A
C3
VCO
098
00-
0
19
Figure 32. Fast Lock Loop Filter Topology 2
SPUR MECHANISMS
This section describes the three different spur mechanisms that
arise with a fractional-N synthesizer and how to minimize them
in the ADF4351.
Fractional Spurs
The fractional interpolator in the ADF4351 is a third-order
Σ-Δ modulator with a modulus (MOD) that is programmable
to any integer value from 2 to 4095. In low spur mode (dither
on), the minimum allowable value of MOD is 50. The Σ-Δ
modulator is clocked at the PFD reference rate (fPFD), which
allows PLL output frequencies to be synthesized at a channel
step resolution of fPFD/MOD.
In low noise mode (dither off), the quantization noise from the
Σ-Δ modulator appears as fractional spurs. The interval between
spurs is fPFD/L, where L is the repeat length of the code sequence
in the digital Σ-Δ modulator. For the third-order Σ-Δ modulator
used in the ADF4351, the repeat length depends on the value of
MOD (see Table 7).
Table 7. Fractional Spurs with Dither Off (Low Noise Mode)
MOD Value (Dither Off)
Repeat
Length
Spur Interval
MOD is divisible by 2, but not by 3
2 × MOD
Channel step/2
MOD is divisible by 3, but not by 2
3 × MOD
Channel step/3
MOD is divisible by 6
6 × MOD
Channel step/6
MOD is not divisible by 2, 3, or 6
MOD
Channel step
In low spur mode (dither on), the repeat length is extended
to 221 cycles, regardless of the value of MOD, which makes the
quantization error spectrum look like broadband noise. This
may degrade the in-band phase noise at the PLL output by as
much as 10 dB. For lowest noise, dither off is a better choice,
particularly when the final loop bandwidth is low enough to
attenuate even the lowest frequency fractional spur.
Integer Boundary Spurs
Another mechanism for fractional spur creation is the inter-
actions between the RF VCO frequency and the reference
frequency. When these frequencies are not integer related (the
purpose of a fractional-N synthesizer), spur sidebands appear
on the VCO output spectrum at an offset frequency that corre-
sponds to the beat note, or difference frequency, between an
integer multiple of the reference and the VCO frequency. These
spurs are attenuated by the loop filter and are more noticeable
on channels close to integer multiples of the reference, where
the difference frequency can be inside the loop bandwidth (thus
the name integer boundary spurs).
Reference Spurs
Reference spurs are generally not a problem in fractional-N
synthesizers because the reference offset is far outside the loop
bandwidth. However, any reference feedthrough mechanism
that bypasses the loop may cause a problem. Feedthrough of
low levels of on-chip reference switching noise, coupling to the
VCO, can result in reference spur levels as high as 80 dBc. The
PCB layout must ensure adequate isolation between VCO circuitry
and the input reference to avoid a possible feedthrough path on
the board.
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| ADF4351BCPZ-RL7 | 功能描述:IC SYNTH PLL VCO 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
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| ADF4355-2BCPZ-RL7 | 功能描述:IC INTEGRATED SYNTH/VCO 32LFCSP 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):有效 類型:* PLL:是 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/無 頻率 - 最大值:4.4GHz 分頻器/倍頻器:是/是 電壓 - 電源:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-WFQFN 裸露焊盤，CSP 供應商器件封裝:24-LFCSP-WQ（4x4） 標準包裝:1,500 |
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