參數(shù)資料
型號(hào)： ADF4158CCPZ-RL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 19/36頁(yè)
文件大?。?/td> 0K
描述： IC FRACTION N FREQ SYNT 24LFCSP
標(biāo)準(zhǔn)包裝： 1,500
類型： 分?jǐn)?shù) N 合成器（RF）
PLL： 是
輸入： CMOS，TTL
輸出： 時(shí)鐘
電路數(shù)： 1
比率 - 輸入:輸出： 2:1
差分 - 輸入:輸出： 是/無(wú)
頻率 - 最大： 6.1GHz
除法器/乘法器： 是/是
電源電壓： 2.7 V ~ 3.3 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 24-WFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 24-LFCSP-WQ（4x4）
包裝： 帶卷 (TR)
ADF4158
Data Sheet
Rev. G | Page 26 of 36
Setting Bit DB28 in the R-divider register (Register R2) to 1
enables cycle slip reduction. Note that a 45% to 55% duty cycle
is needed on the signal at the PFD in order for CSR to operate
correctly. The reference divide-by-2 flip-flop can help to provide a
50% duty cycle at the PFD. For example, if a 100 MHz reference
frequency is available and the user wants to run the PFD at
10 MHz, setting the R-divide factor to 10 results in a 10 MHz
PFD signal that is not 50% duty cycle. By setting the R-divide
factor to 5 and enabling the reference divide-by-2 bit, a 50%
duty cycle 10 MHz signal can be achieved.
Note that the cycle slip reduction feature can only be operated
when the phase detector polarity setting is positive (DB6 in
Register R3). It cannot be used if the phase detector polarity is
negative.
MODULATION
The ADF4158 can operate in frequency shift keying (FSK) or
phase shift keying (PSK) mode.
Frequency Shift Keying (FSK)
FSK is implemented by setting the ADF4158 N-divider up for
the center frequency and then toggling the TXDATA pin. The
deviation from the center frequency is set by
fDEV = (fPFD/225) × (DEV × 2DEV_OFFSET)
(7)
where:
fPFD is the PFD frequency.
DEV is a 16-bit word.
DEV_OFFSET is a 4-bit word.
The ADF4158 implements this by incrementing or decrementing
the set N-divide value by DEV × 2DEV_OFFSET.
Phase Shift Keying (PSK)
When the ADF4158 is set up in PSK mode, it is possible to
toggle the output phase of the ADF4158 between 0° and 180°.
The TXDATA pin controls the phase.
FSK Settings Worked Example
For example, take an FSK system operating at 5.8 GHz, with a
25 MHz PFD, 250 kHz deviation and DEV_OFFSET = 4.
Rearrange Equation 4 as follows
OFFSET
DEV
PFD
DEV
f
DEV
_
25
2
×
=
(8)
52
.
971
,
20
2
MHz
25
kHz
250
4
25
=
×
=
DEV
The DEV value is rounded to 20,972. Toggling the TXDATA pin
causes the frequency to hop between ±250 kHz frequencies
from the programmed center frequency.
WAVEFORM GENERATION
The ADF4158 is capable of generating four types of waveforms
in the frequency domain: single ramp burst, single sawtooth
burst, sawtooth ramp, and triangular ramp. Figure 31 through
Figure 34 show the types of waveforms available.
F
RE
Q
UE
NCY
TIME
08728-
022
Figure 31. Single Ramp Burst
F
RE
Q
UE
NCY
TIME
08728-
021
Figure 32. Single Sawtooth Burst
F
RE
Q
UE
NCY
TIME
08728-
019
Figure 33. Sawtooth Ramp
F
RE
Q
UE
NCY
TIME
08728-
020
Figure 34. Triangular Ramp
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參數(shù)描述
ADF4158WCCPZ 功能描述:IC FRAC-N FREQ SYNTH 24LFCSP 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:分?jǐn)?shù) N 合成器（RF） PLL:是 輸入:CMOS，TTL 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/無(wú) 頻率 - 最大值:6.1GHz 分頻器/倍頻器:是/是 電壓 - 電源:2.7 V ~ 3.3 V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-WFQFN 裸露焊盤 供應(yīng)商器件封裝:24-LFCSP-WQ（4x4） 標(biāo)準(zhǔn)包裝:1
ADF4158WCCPZ-RL7 功能描述:IC FRAC-N FREQ SYNTH 24LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無(wú) 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND
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ADF4159CCPZ-RL7 制造商:Analog Devices 功能描述:Fractional-N Frequency Synthesizer 24-Pin LFCSP EP T/R 制造商:Analog Devices 功能描述:13GHZ FAST RAMP DIRECT MOD FRAC N PLL - Tape and Reel 制造商:Analog Devices Inc. 功能描述:Phase Locked Loops - PLL
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