參數(shù)資料
型號: ADF4158CCPZ-RL7
廠商: Analog Devices Inc
文件頁數(shù): 1/36頁
文件大?。?/td> 0K
描述: IC FRACTION N FREQ SYNT 24LFCSP
標準包裝: 1,500
類型: 分數(shù) N 合成器(RF)
PLL:
輸入: CMOS,TTL
輸出: 時鐘
電路數(shù): 1
比率 - 輸入:輸出: 2:1
差分 - 輸入:輸出: 是/無
頻率 - 最大: 6.1GHz
除法器/乘法器: 是/是
電源電壓: 2.7 V ~ 3.3 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 24-WFQFN 裸露焊盤,CSP
供應商設(shè)備封裝: 24-LFCSP-WQ(4x4)
包裝: 帶卷 (TR)
Direct Modulation/Waveform Generating,
6.1 GHz Fractional-N Frequency Synthesizer
Data Sheet
Rev. G
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
2010–2014 Analog Devices, Inc. All rights reserved.
FEATURES
Radio frequency (RF) bandwidth to 6.1 GHz
25-bit fixed modulus allows subhertz frequency resolution
Frequency and phase modulation capability
Sawtooth and triangular waveforms in the frequency domain
Parabolic ramp
Ramp superimposed with FSK
Ramp with 2 different sweep rates
Ramp delay
Ramp frequency readback
Ramp interruption
2.7 V to 3.3 V power supply
Separate VP allows extended tuning voltage
Programmable charge pump currents
3-wire serial interface
Digital lock detect
Power-down mode
Cycle slip reduction for faster lock times
Switched bandwidth fast-lock mode
Qualified for automotive applications
APPLICATIONS
Frequency modulated continuous wave (FMCW) radar
Communications test equipment
GENERAL DESCRIPTION
The ADF4158 is a 6.1 GHz fractional-N frequency synthesizer
with direct modulation and waveform generation capability. It
contains a 25-bit fixed modulus, allowing subhertz resolution at
6.1 GHz. It consists of a low noise digital phase frequency
detector (PFD), a precision charge pump, and a programmable
reference divider. There is a sigma-delta (Σ-Δ) based fractional
interpolator to allow programmable fractional-N division. The
INT and FRAC registers define an overall N-divider as N = INT +
(FRAC/225).
The ADF4158 can be used to implement frequency shift keying
(FSK) and phase shift keying (PSK) modulation. There are also
a number of frequency sweep modes available that generate
various waveforms in the frequency domain, for example,
sawtooth and triangular waveforms. The ADF4158 features
cycle slip reduction circuitry, which leads to faster lock times,
without the need for modifications to the loop filter.
Control of all on-chip registers is via a simple 3-wire interface.
The device operates with a power supply ranging from 2.7 V to
3.3 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
LOCK
DETECT
N-COUNTER
CP
SW1
REFERENCE
DATA
LE
TXDATA
CE
32-BIT
DATA
REGISTER
CLK
REFIN
AVDD
AGND
VDD
DGND
RDIV
NDIV
DGND
CPGND
DVDD
VP
RSET
RFINA
RFINB
OUTPUT
MUX
+
HIGH-Z
PHASE
FREQUENCY
DETECTOR
ADF4158
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
MODULUS
225
FRACTION
REG
INTEGER
REG
CSR
×2
DOUBLER
5-BIT
R-COUNTER
÷2
DIVIDER
CHARGE
PUMP
MUXOUT
08728-
001
FLO SWITCH
SW2
Figure 1.
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