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參數(shù)資料
| 型號(hào)： | ADF4108BCPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 2/20頁(yè) |
| 文件大小： | 0K |
| 描述： | IC PLL FREQUENCY SYNTH 20-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | 時(shí)鐘/頻率合成器，RF |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無(wú) |
| 頻率 - 最大： | 8GHz |
| 除法器/乘法器： | 無(wú)/無(wú) |
| 電源電壓： | 3.2 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 20-LFCSP-VQ |
| 包裝： | 帶卷 (TR) |
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ADF4108
Data Sheet
Rev. E | Page 10 of 20
PHASE FREQUENCY DETECTOR AND
CHARGE PUMP
The phase frequency detector (PFD) takes inputs from the R
counter and N counter (N = BP + A) and produces an output
proportional to the phase and frequency difference between
them. Figure 13 is a simplified schematic. The PFD includes a
programmable delay element that controls the width of the
antibacklash pulse. This pulse ensures that there is no dead zone
in the PFD transfer function and minimizes phase noise and
reference spurs. Two bits in the reference counter latch, ABP2
and ABP1, control the width of the pulse (see Figure 16). Use of
the minimum antibacklash pulse width is not recommended.
HI
D1
D2
Q1
Q2
CLR2
CP
U1
U2
UP
DOWN
ABP2
ABP1
CPGND
U3
R DIVIDER
PROGRAMMABLE
DELAY
N DIVIDER
VP
CHARGE
PUMP
CLR1
06015-
019
Figure 13. PFD Simplified Schematic and Timing (in Lock)
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4108 allows the user to access
various internal points on the chip. The state of MUXOUT is
controlled by M3, M2, and M1 in the function latch. Figure 18
shows the full truth table. Figure 14 shows the MUXOUT section
in block diagram form.
Lock Detect
MUXOUT can be programmed for two types of lock detect: digital
lock detect and analog lock detect.
Digital lock detect is active high. When the lock detect precision
(LDP) bit in the R counter latch is set to 0, digital lock detect is
set high when the phase error on three consecutive phase detector
(PD) cycles is less than 15 ns. With LDP set to 1, five consecutive
cycles of less than 15 ns are required to set the lock detect. It stays
set high until a phase error of greater than 25 ns is detected on any
subsequent PD cycle.
The N-channel open-drain analog lock detect should be operated
with an external pull-up resistor of 10 k nominal. When lock
has been detected, this output is high with narrow, low going
pulses.
DGND
DVDD
CONTROL
MUX
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
SDOUT
MUXOUT
06015-
020
Figure 14. MUXOUT Circuit
INPUT SHIFT REGISTER
The ADF4108 digital section includes a 24-bit input shift register, a
14-bit R counter, and a 19-bit N counter, comprising a 6-bit A
counter and a 13-bit B counter. Data is clocked into the 24-bit
shift register on each rising edge of CLK. The data is clocked in
MSB first. Data is transferred from the shift register to one of
four latches on the rising edge of LE. The destination latch is
determined by the state of the two control bits (C2, C1) in the
shift register. These are the 2 LSBs, DB1 and DB0, as shown in
the timing diagram of Figure 2. The truth table for these bits is
shown in Table 5.
Figure 15 shows a summary of how the latches are programmed.
Table 5. C2 and C1 Truth Table
Control Bits
Data Latch
C2
C1
0
R counter
0
1
N counter (A and B)
1
0
Function latch (including prescaler)
1
Initialization latch
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