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參數(shù)資料
| 型號： | ADF4108BCPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL FREQUENCY SYNTH 20-LFCSP |
| 標準包裝： | 1,500 |
| 類型： | 時鐘/頻率合成器，RF |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 8GHz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 3.2 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 20-LFCSP-VQ |
| 包裝： | 帶卷 (TR) |
ADF4108
Data Sheet
Rev. E | Page 18 of 20
INTERFACING
The ADF4108 has a simple SPI-compatible serial interface for
writing to the device. CLK, DATA, and LE control the data transfer.
When LE (latch enable) goes high, the 24 bits that have been
clocked into the input register on each rising edge of CLK are
transferred to the appropriate latch. See Figure 2 for the timing
diagram and Table 5 for the latch truth table.
The maximum allowable serial clock rate is 20 MHz. This means
that the maximum update rate possible for the device is 833 kHz or
one update every 1.2 s. This is certainly more than adequate for
systems that have typical lock times in hundreds of microseconds.
ADUC812 INTERFACE
Figure 20 shows the interface between the ADF4108 and the
on an 8051 core, this interface can be used with any 8051-based
microcontroller. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4108 needs a
24-bit word. This is accomplished by writing three 8-bit bytes
from the MicroConverter to the device. When the third byte
has been written, the LE input should be brought high to
complete the transfer.
On first applying power to the ADF4108, it needs four writes
(one each to the initialization latch, function latch, R counter
latch, and N counter latch) for the output to become active.
I/O port lines on the ADuC812 are also used to control power-
down (CE input) and to detect lock (MUXOUT configured as
lock detect and polled by the port input).
When operating in the mode described, the maximum SCLOCK
rate of the ADuC812 is 4 MHz. This means that the maximum
rate at which the output frequency can be changed is 166 kHz.
CLK
DATA
LE
CE
MUXOUT
(LOCK DETECT)
MOSI
ADF4108
SCLOCK
I/O PORTS
ADuC812
06015-
026
Figure 20. ADuC812 to ADF4108 Interface
ADSP-21xx INTERFACE
Figure 21 shows the interface between the ADF4108 and the
ADSP-21xx digital signal processor. The ADF4108 needs a 24-bit
serial word for each latch write. The easiest way to accomplish
this using the ADSP-21xx family is to use the autobuffered transmit
mode of operation with alternate framing. This provides a means
for transmitting an entire block of serial data before an interrupt is
generated. Set up the word length for 8 bits and use three memory
locations for each 24-bit word. To program each 24-bit latch,
store the three 8-bit bytes, enable the autobuffered mode, and
then write to the transmit register of the DSP. This last operation
initiates the autobuffer transfer.
CLK
DATA
LE
CE
MUXOUT
(LOCK DETECT)
MOSI
ADF4108
SCLOCK
I/O FLAGS
ADSP-21xx
TFS
06015-
027
Figure 21. ADSP-21xx to ADF4108 Interface
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