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參數(shù)資料
| 型號： | ADF4108BCPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL FREQUENCY SYNTH 20-LFCSP |
| 標準包裝： | 1,500 |
| 類型： | 時鐘/頻率合成器，RF |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 8GHz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 3.2 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 20-LFCSP-VQ |
| 包裝： | 帶卷 (TR) |
Data Sheet
ADF4108
Rev. E | Page 7 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
06
015
-003
1
9
R
S
E
T
2
0
C
P
1
8
V
P
1
7
D
V
D
1
6
D
V
D
ADF4108
15 MUXOUT
14 LE
13 DATA
12 CLK
11 CE
CPGND 1
AGND 2
AGND 3
RFINB 4
RFINA 5
TOP VIEW
(Not to Scale)
6
7
8
DG
ND
9
DG
ND
10
AV
DD
AV
DD
RE
F
IN
NOTES
1. THE EXPOSED PAD MUST BE
CONNECTED TO AGND.
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
CPGND
Charge Pump Ground. This is the ground return path for the charge pump.
2, 3
AGND
Analog Ground. This is the ground return path of the prescaler.
4
RFINB
Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a small bypass
capacitor, typically 100 pF. See Figure 11.
5
RFINA
Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.
6, 7
AVDD
Analog Power Supply. This voltage may range from 3.2 V to 3.6 V. Decoupling capacitors to the analog ground
plane should be placed as close as possible to this pin. AVDD must be the same value as DVDD.
8
REFIN
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of
100 kΩ. See Figure 10. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled.
9, 10
DGND
Digital Ground.
11
CE
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-state
mode. Taking the pin high powers up the device, depending on the status of the power-down bit, F2.
12
CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the
24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
13
DATA
Serial Data Input. The serial data is loaded MSB first with the 2 LSBs being the control bits. This input is a high
impedance CMOS input.
14
LE
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four
latches, the latch being selected using the control bits.
15
MUXOUT
This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be
accessed externally.
16, 17
DVDD
Digital Power Supply. This may range from 3.2 V to 3.6 V. Decoupling capacitors to the digital ground plane should
be placed as close as possible to this pin. DVDD must be the same value as AVDD.
18
VP
Charge Pump Power Supply. This voltage should be greater than or equal to VDD. In systems where VDD is 3.3 V, it
can be set to 5 V and used to drive a VCO with a tuning range of up to 5 V.
19
RSET
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The nominal
voltage potential at the RSET pin is 0.66 V. The relationship between ICP and RSET is
SET
MAX
CP
R
I
25.5
with RSET = 5.1 kΩ, ICP MAX = 5 mA.
20
CP
Charge Pump Output. When enabled, this pin provides ±ICP to the external loop filter, which in turn drives the
external VCO.
EP
Exposed Pad. The exposed pad must be connected to AGND.
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